參數(shù)資料
型號(hào): TC1301B-FFAVMFTR
元件分類: 固定正電壓多路輸出LDO穩(wěn)壓器
英文描述: DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, PDSO8
封裝: 3 X 3 MM, 1 MM HEIGHT, PLASTIC, DFN-8
文件頁(yè)數(shù): 7/26頁(yè)
文件大小: 1080K
代理商: TC1301B-FFAVMFTR
2003 Microchip Technology Inc.
DS21798A-page 15
TC1301A/B
5.10
TC1301A SHDN2 Timing
VOUT1 will rise independent of the level of SHDN2 for
the TC1301A. Figure 5-1 is used to define the wake-up
time from shutdown (tWK) and the settling time (tS). The
wake-up time is dependant upon the frequency of
operation. The faster the SHDN pin is pulsed, the
shorter the wake-up time will be.
FIGURE 5-1:
TC1301A Timing.
5.11
TC1301B SHDN1 / SHDN2 Timing
For the TC1301B, the SHDN1 input pin is used to
control VOUT1. The SHDN2 input pin is used to control
VOUT2, independent of the logic input on SHDN1.
FIGURE 5-2:
TC1301B Timing.
5.12
VDET and RESET Operation
The TC1301A/B integrates an independent voltage
reset monitor that can be used for low battery input
voltage detection or a microprocessor power-on reset
(POR) function. The input voltage for the detector is
different for the TC1301A than it is for the TC1301B.
For the TC1301A, the input voltage to the detector is
pin 8, or the VDET pin. For the TC1301B, the input
voltage to the detector is internally connected to the
output of LDO #1 (VOUT1). The detected voltage is
sensed and compared to an internal threshold. When
the voltage on the VDET pin is below the threshold
voltage, the RESET output pin is low. When the voltage
on the VDET pin rises above the voltage threshold, the
RESET output will remain low for typically 300 ms
(RESET time out period). After the RESET time-out
period, the RESET output voltage will transition from
the low output state to the high output state if the
detected voltage pin remains above the threshold
voltage.
The RESET output will be driven low within 180 s of
VDET going below the RESET voltage threshold. The
RESET output will remain valid for detected voltages
greater than 1.2V overtemperature.
5.13
TC1301A RESET Timing
Figure 5-3 shows the RESET timing waveforms for the
TC1301A. This diagram is also used to define the
RESET active time-out period (tRPU) and the VDET
RESET delay time (tRPD).
FIGURE 5-3:
TC1301A RESET Timing.
VIN
SHDN2
VOUT1
VOUT2
twk
ts
SHDN2
SHDN1
VIN
VOUT1
twk
ts
VOUT2
RESET Time
TRPD
VTH
VDET
RESET
1V
VOL
VOH
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