參數(shù)資料
型號: TC4467MJD
廠商: TelCom Semiconductor, Inc.
英文描述: LOGIC-INPUT CMOS QUAD DRIVERS
中文描述: 邏輯輸入的CMOS四驅(qū)動器
文件頁數(shù): 3/9頁
文件大?。?/td> 120K
代理商: TC4467MJD
4-263
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
LOGIC-INPUT CMOS
QUAD DRIVERS
TC4467
TC4468
TC4469
Symbol
Input
V
IH
V
IL
I
IN
Output
V
OH
V
OL
R
O
I
PK
I
Parameter
Test Conditions
Min
Typ
Max
Unit
Logic 1, High Input Voltage
Logic 0, Low Input Voltage
Input Current
(Note 3)
(Note 3)
0V
V
IN
V
DD
2.4
– 10
0.8
10
V
V
μ
A
High Output Voltage
Low Output Voltage
Output Resistance
Peak Output Current
Latch-Up Protection
Withstand Reverse Current
I
LOAD
= 100
μ
A (Note 1)
I
LOAD
= 10 mA (Note 1)
I
OUT
= 10 mA, V
DD
= 18V
V
DD
– 0.025
500
20
1.2
0.30
30
V
V
A
mA
4.5V
V
DD
16V
Switching Time
t
R
t
F
t
D1
t
D2
Power Supply
I
S
I
S
NOTES:
1. Totem-pole outputs should not be paralleled because the propagation delay differences from one to the other could cause one driver to
drive high a few nanoseconds before another. The resulting current spike, although short, may decrease the life of the device.
2. When driving all four outputs simultaneously in the same direction, V
DD
shall be limited to 16V. This reduces the chance that internal
dv/dt will cause high-power dissipation in the device.
3. The input threshold has about 50 mV of hysteresis centered at approximately 1.5V. Slow moving inputs will force the device to
dissipate high peak currents as the input transitions through this band. Input rise times should be kept below 5
μ
s to avoid high internal
peak currents during input transitions. Static input levels should also be maintained above the maximum or below the minimum input
levels specified in the "Electrical Characteristics" to avoid increased power dissipation in the device.
Rise Time
Fall Time
Delay Time
Delay Time
Figure 1
Figure 1
Figure 1
Figure 1
50
50
100
100
nsec
nsec
nsec
nsec
Power Supply Current
Power Supply Voltage
4.5
8
18
mA
V
Note 2
ELECTRICAL CHARACTERISTICS:
Measured throughout operating temperature range with 4.5V
V
DD
18V,
unless otherwise specified.
PIN CONFIGURATIONS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
2A
2B
3A
3B
GND
V
1Y
2Y
3Y
4Y
4B
4A
DD
1
2
3
4
5
6
7
8
16
13
12
11
10
9
1A
1B
2A
2B
3A
3B
GND
GND
V
1Y
2Y
3Y
4Y
4B
4A
DD
V
DD
15
14
TC4467/8/9
TC4467/8/9
16-Pin SOIC (Wide)
14-Pin Plastic DIP/CerDIP
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