參數(shù)資料
型號: TC500CPE
廠商: Microchip Technology Inc.
英文描述: Precision Analog Front Ends
中文描述: 精密模擬前端
文件頁數(shù): 1/17頁
文件大?。?/td> 209K
代理商: TC500CPE
3-19
TELCOM SEMICONDUCTOR, INC.
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PRECISION ANALOG FRONT ENDS
FEATURES
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Precision (up to 17 Bits) A/D Converter "Front End"
3-Pin Control Interface to Microprocessor
Flexible: User Can Trade-Off Conversion Speed
for Resolution
Single Supply Operation (TC510/514)
4 Input, Differential Analog MUX (TC514)
Automatic Input Voltage Polarity Detection
Low Power Dissipation ...........TC500/500A: 10mW
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TC510/514: 18mW
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Wide Analog Input Range .......
±
4.2V (TC500A/510)
Directly Accepts Bipolar and Differential Input
Signals
GENERAL DESCRIPTION
The TC500/500A/510/514 family are precision analog
front ends that implement dual slope A/D converters having
a maximum resolution of 17 bits plus sign. As a minimum,
each device contains the integrator, zero crossing compara-
tor and processor interface logic. The TC500 is the base
(16 bit max) device and requires both positive and negative
power supplies. The TC500A is identical to the TC500,
except it has improved linearity allowing it to operate to a
maximum resolution of 17 bits. The TC510 adds an on-
board negative power supply converter for single supply
operation. The TC514 adds both a negative power supply
converter and a 4 input differential analog multiplexer.
Each device has the same processor control interface
consisting of 3 wires: control inputs A and B and zero-
crossing comparator output (CMPTR). The processor ma-
nipulates A, B to sequence the TC5xx through four phases
of conversion: Auto Zero, Integrate, Deintegrate and Inte-
grator Zero. During the Auto Zero phase, offset voltages in
the TC5xx are corrected by a closed-loop feedback mecha-
nism. The input voltage is applied to the integrator during the
Integrate phase. This causes an integrator output dv/dt
directly proportional to the magnitude of the input voltage.
The higher the input voltage, the greater the magnitude of
the voltage stored on the integrator during this phase. At the
start of the Deintegrate phase, an external voltage reference
is applied to the integrator, and at the same time, the external
host processor starts its on-board timer.
The processor main-
FUNCTIONAL BLOCK DIAGRAM
LEVEL
SHIFT
CONTROL LOGIC
ANALOG
SWITCH
CONTROL
SIGNALS
ACOM
V+
BUF
CAZ
BUFFER
INTEGRATOR
SWR
SWIZ
CMPTR 1
+
CMPTR 2
CMPTR
OUTPUT
DGND
CONTROL LOGIC
SW1
TC500
TC500A
TC510
TC514
CREF
C+
SWR
C–
CAZ
RINT
CINT
CINT
SWRI
+
SWRI
+
SWRI
SWRI
SWZ
SWI
SWZ
VS
OSC
+
+
PHASE
DECODING
LOGIC
POLARITY
DETECTION
DC-TO-DC
CONVERTER
(TC510 & TC514)
+
A B
0
0
1
1
0
1
0
1
ZERO INTEGRATOR OUTPUT
AUTO-ZERO
SIGNAL INTEGRATE
DEINTEGRATE
V–
V–
C–
1.0
μ
F
1.0
μ
F
VSS
(TC500
TC500A)
SWI
B
A
A0
A1
DIF.
MUX
(TC514)
CH1 +
CH2 +
CH3 +
CH4 +
CH1 –
CH2 –
CH3 –
CH4 –
CAP– CAP+
CONVERTER STATE
TC500
TC500A
TC510
TC514
TC500/A/510/514-3 10/3/96
ORDERING INFORMATION
Part No.
Package
Temp. Range
TC500ACOE
T
C500ACPE
TC500COE
TC500CPE
TC510COG
TC510CPF
TC514COI
TC514CPJ
TC500EV
16-Pin SOIC
16-Pin Plastic DIP (Narrow)
16-Pin SOIC
16-Pin Plastic DIP (Narrow)
24-Pin SOIC
24-Pin Plastic DIP (300 Mil.)
28-Pin SOIC
28-Pin Plastic DIP (300 Mil.)
Evaluation Kit for TC500/500A/510/514
0
°
C to +70
°
C
0
°
C to +70
°
C
0
°
C to +70
°
C
0
°
C to +70
°
C
0
°
C to +70
°
C
0
°
C to +70
°
C
0
°
C to +70
°
C
0
°
C to +70
°
C
EVALUATION
KIT
AVAILABLE
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