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參數(shù)資料
| 型號： | TC520A |
| 廠商： | TelCom Semiconductor, Inc. |
| 英文描述： | SERIAL INTERFACE ADAPTER FOR TC500 A/D CONVERTER FAMILY |
| 中文描述： | 串行接口適配器TC500的A / D轉(zhuǎn)換器系列 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 81K |
| 代理商： | TC520A |
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TELCOM SEMICONDUCTOR, INC.
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TC520A
SERIAL INTERFACE ADAPTER FOR
TC500 A/D CONVERTER FAMILY
a range of AZ = INT = 256 counts to 65536 counts). (See
Figure 2). The LOAD VALUE sets the number of counts for
boththe AZ and INT phases and directly affects resolution
and speed of conversion. The greaterthe number of counts
allowed for AZ and INT; the greaterthe A/D resolution, but
the slowerthe conversion speed.
The time period required for the D
INT
phase is a function
of the amount of voltage stored on the integrator during the
INT phase, and the value of V
REF
. The D
INT
phase is initiated
by the TC520A immediately after the INT phase, and termi-
nated when the TC5xx A/D converter changes the state of
the CMPTR input of the TC520A (indicating a zero crossing).
In general, the maximum number of counts chosen for D
INT
is twice that of INT (with V
REF
chosen at V
IN
(max)/2).
Choosing these values guarantees a full count (maximum
resolution) during D
INT
when V
IN
= V
IN
(max).
The IZ phase is initiated immediately following the D
INT
phase maintained until the CMPTR input transitions high.
This indicates the integrator is initialized and ready for
another conversion cycle. This phase typically takes 2msec.
Serial Port Control Signals
Communication to and from the TC520A is accom-
plished over a 3 wire serial port. Data is clocked into D
IN
on
the rising edge of D
CLK
and clocked out of D
OUT
on the falling
edge of D
CLK
. READ must be low to read from the serial port
and can be taken high at any time, which terminates the read
cycle, and releases D
OUT
to a high impedance state. Con-
version data is shifted to the processor from D
OUT
in the
following order: Overrange bit (which can also be used as
the 17th data bit), Polarity bit, conversion data (MSB first).
APPLICATIONS
TC500 Series A/D Converter Component Selection
The TC500/500A/510/514 data sheet details the equa-
tions necessary to calculate values for integration resistor
(R
INT
) and capacitor (C
INT
); auto zero and reference capaci-
tors C
REF
and C
AZ
and voltage reference V
REF
. All equations
apply when using the TC520A, except integration time (T
INT
)
and Autozero time (T
AZ
) are functions of the SYSCLK period
(timebase frequency and LOAD VALUE). TelCom offers a
ready-to-use TC5xx A/D converter design tool on a 3 1/2
inch diskette (Windows format). The TC500 Design Spread-
sheet is an Excel-based spreadsheet that calculates values
for all components as well as the TC520A LOAD VALUE. It
also calculates overall converter performance such as noise
rejection, converter speed, etc. This software is included in
the TC500EV hardware evaluation kit and is also available
free of charge from your local TelCom representative.
TC520A Initialization
Initialization of the TC520A consists of:
(1) Power-On RESET of the TC500/520A (forcing the
TC520A into an AZ phase).
(2) Initializing the TC520A LOAD VALUE.
Power-On RESET
The TC520A powers-up with A, B = 00 (IZ Phase),
awaiting a high logic state on CMPTR, which must be
initiated by forcing the TC520A into the AZ phase. This can
be accomplished in one of two ways:
(1) External hardware (processor or logic) can momen-
tarily taking LOAD or CE low for a minimum of 100
msec (tAZI); or
(2) A .01
μ
F RESET capacitor can be connected from
CE to V
CC
to generate a power-on pulse on CE.
Load Value Initialization
The LOAD VALUE is the preset value (high byte of the
SYSCLK timing counter) which determines the number of
counts allocated to the AZ and INT phases of conversion.
This value can be calculated using the TC520A spreadsheet
within the TC500 Design Spreadsheet software, or can be
setup as shown in the following example:
(1)
Select V
REF
, TD
INT
Choose the TC5xx A/D converter reference voltage
(V
REF
) to be half of the maximum A/D converter
input voltage. For example, if V
IN
max = 2.5V;
choose V
REF
= 1.75V. This forces the maximum de-
integration time (TD
INT
) to be equal to twice the
maximum integration time (T
INT
) ensuring a full
count (maximum resolution) during D
INT
.
(2)
Calculate T
INT
The TC520A counter length is 16 bits (65536).
Allowing the full 65536 counts for TD
INT
results in a
maximum T
INT
= 65536/2 or 32768.
(3)
Select SYSCLK Frequency
SYSCLK frequency directly affects conversion time.
The faster the SYSCLK, the faster the conversion
time. The upper limit SYSCLK frequency is deter-
mined by the worst case delay of the TC500 com-
parator (which for the TC500 and TC500A is
3.2
μ
sec). While a faster value for SYSCLK can be
used, operation is optimized (error minimized) by
choosing a SYSCLK period (1/SYSCLK frequency)
that is greater than 3.2
μ
sec. Choosing T
SYSCLK
=
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