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參數(shù)資料
| 型號(hào)： | TC530CPJ |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 5V Precision Data Acquisition Subsystems |
| 中文描述： | 5V的高精度數(shù)據(jù)采集子系統(tǒng) |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 158K |
| 代理商： | TC530CPJ |
3-52
TELCOM SEMICONDUCTOR, INC.
5V PRECISION DATA ACQUISITION
SUBSYSTEMS
TC530
TC534
PIN DESCRIPTION
(Cont.)
Pin No.
(TC530
28-Pin
PDIP, 300 Mil.)
SOIC)
Pin No.
(TC530
28-Pin
Pin No
(TC534
40-Pin
PDIP)
Pin No.
(TC534
44-Pin
PQFP)
Symbol
Description
15
15
22
19
OSC
IN
Analog Input. This pin connects to the other side of the
crystal described in OSC
OUT
above. The TC530/534 may also
be clocked from an external frequency source connected to
this pin. The external frequency source must be a pulse wave
form with a minimum 30% duty cycle and rise and fall times
15nsec (Max). If an external frequency source is used, OSC
OUT
must be left floating. A maximum operating frequency of 2MHz
(crystal) or 4MHz (external clock source) is permitted.
Logic Level Output. Serial port data output pin. This pin is
enabled only when R/W is high.
Logic Input, Positive and Negative Edge Triggered. Serial port
clock. When R/W is high, serial data is clocked out of the
TC530/534A (on D
OUT
) at each HIGH-to-LOW transition of
D
CLK
. A/D initialization data (LOAD VALUE) is clocked into the
TC530/534 (on D
IN
) at each LOW-to-HIGH transition of D
CLK
. A
maximum serial port D
CLK
frequency of 3MHz is permitted.
Logic Level Input. Serial port input pin. The A/D converter
integration time (T
INT
) and Auto Zero time (T
AZ
) values are
determined by the LOAD VALUE byte clocked into this pin.
This initialization must take place at power up, and can be
rewritten (or modified and rewritten) at any time. The LOAD
VALUE is clocked into D
IN
MSB first.
Logic Level Input. This pin must be brought low to perform a
write to the serial port (e.g. initialize the A/D converter). The
D
OUT
pin of the serial port is enabled only when this pin is high.
Open Drain Output. End-of-Conversion (EOC) is asserted
any time the TC530/534 is in the AZ phase of conversion. This
occurs when either the TC530/534 initiates a normal AZ phase,
or when RESET is pulled high. EOC is returned high when the
TC530/534 exits AZ. Since EOC is driven low immediately
following completion of a conversion cycle, it can be used as
a DATA READY processor interrupt.
Logic Level Input. It is necessary to force the TC530/534 into
the Auto Zero phase when power is initially applied. This is
accomplished by momentarily taking RESET high. Using an I/O
port line from the microprocessor, or by applying an external
system reset signal, or by
connecting
a 0.01
μ
F capacitor from
the RESET input to V
SS
.
16
16
23
20
D
OUT
17
17
24
21
D
CLK
18
18
25
22
D
IN
19
19
26
23
R/W
20
20
27
24
EOC
21
21
30
28
RESET
Conversions are performed continuously as long as RESET is
low and conversion is halted when RESET is high. RESET
may therefore be used in a complex system to momentarily
suspend conversion (for example while the address lines of an
input multiplexer are changing state). In this case, RESET
should be pulled high only when the EOC is LOW to avoid
excessively long integrator discharge times which could result in
erroneous conversion (see Applications Section).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TC530 | 5V Precision Data Acquisition Subsystems |
| TC534 | 5V Precision Data Acquisition Subsystems |
| TC534CPL | 5V Precision Data Acquisition Subsystems |
| TC530COI | 5V Precision Data Acquisition Subsystems |
| TC534CKW | 5V Precision Data Acquisition Subsystems |
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