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參數資料
| 型號： | TC530CPJ |
| 廠商： | TelCom Semiconductor, Inc. |
| 英文描述： | 5V PRECISION DATA ACQUISITION SUBSYSTEMS |
| 中文描述： | 5V的高精度數據采集的子系統(tǒng) |
| 文件頁數： | 8/15頁 |
| 文件大?。?/td> | 158K |
| 代理商： | TC530CPJ |
3-54
TELCOM SEMICONDUCTOR, INC.
30
20
10
0
0.1/T
1/T
10/T
INPUT FREQUENCY
N
T = MEASUREMENT
PERIOD
EOC
t
DR
AZ
Updated Data
Ready
Updated Data
Ready
INT
D
INT
IZ
AZ
Conversion
Phase
Data to Serial
Port Transmit
Register
Figure 3. Integrating Converter Normal Mode Rejection
Figure 2. A/D Converter Timing
DETAILED DESCRIPTION
Dual Slope Integrating Converter
The TC530/534 dual slope converter operates by inte-
grating the input signal for a fixed time period, then applying
an opposite polarity reference voltage while timing the
period (counting clocks pulses) for the integrator output to
cross 0V (deintegrating). The resulting count is read as
conversion data.
A simple mathematical expression that describes dual
slope conversion is:
(1) Integrate Voltage = Deintegrate Voltage
∫
(2)
t
INT
0
∫
t
DINT
0
1/R
INT
C
INT
V
IN
(t)dt = 1/R
INT
C
INT
V
REF
from which:
(3)
[
]
(t
INT
)
(V
IN
)
= (V
REF
)
(R
INT
)(C
INT
)
[
]
(t
DINT
)
(R
INT
)(C
INT
)
and therefore:
(4)
V
IN
= V
REF
[ ]
t
DINT
t
INT
where: V
REF
= Reference Voltage
t
INT
= Integrate Time
t
DINT
= Reference Voltage Deintegrate Time
Inspection of equation (4) shows dual slope converter
accuracy is unrelated to integrating resistor and capacitor
values, as long as they are stable throughout the measure-
ment cycle. This measurement technique is inherently
ratiometric (i.e., the ratio between the t
INT
and t
DINT
times is
equal to the ratio between V
IN
and V
REF
).
Another inherent benefit is noise immunity. Input noise
spikes are integrated (or averaged to zero) during the
integration period. The integrating converter has a noise
immunity with an attenuation rate of at least –20dB per
decade. Interference signals with frequencies at integral
multiples of the integration period are, for the most part,
completely removed. For this reason, the integration period
of the converter is often established to reject 50/60Hz line
noise. The ability to reject such noise is shown by the plot of
Figure 3.
In addition to the two phases required for dual slope
measurement (Integrate and Deintegrate), the TC530/534
performs two additional adjustments to minimize measure-
ment error due to system offset voltages. The resulting four
internal operations (conversion phases) performed each
measurement cycle are: Auto Zero (AZ), Integrator Output
Zero (IZ), Input Integrate (INT) and Reference Deintegrate
(D
INT
). The AZ and IZ phases compensate for system offset
errors and the INT and D
INT
phases perform the actual A/D
conversion.
5V PRECISION DATA ACQUISITION
SUBSYSTEMS
TC530
TC534
相關PDF資料 |
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| TC530COI | 5V PRECISION DATA ACQUISITION SUBSYSTEMS |
| TC534CKW | 5V PRECISION DATA ACQUISITION SUBSYSTEMS |
| TC54VC4202ECB | VOLTAGE DETECTOR |
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