參數(shù)資料
型號： TC7107ILW713
元件分類： ADC
英文描述： 1-CH DUAL-SLOPE ADC, PARALLEL ACCESS, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 33/34頁
文件大?。?/td> 482K
代理商： TC7107ILW713
TC7106/A/TC7107/A
DS21455D-page 8
2008 Microchip Technology Inc.
3.0
DETAILED DESCRIPTION
(All Pin designations refer to 40-Pin PDIP.)
3.1
Dual Slope Conversion Principles
The TC7106A and TC7107A are dual slope, integrating
Analog-to-Digital Converters. An understanding of the
dual slope conversion technique will aid in following the
detailed operation theory.
The conventional dual slope converter measurement
cycle has two distinct phases:
Input Signal Integration
Reference Voltage Integration (De-integration)
The input signal being converted is integrated for a
fixed time period (TSI). Time is measured by counting
clock pulses. An opposite polarity constant reference
voltage is then integrated until the integrator output
voltage returns to zero. The reference integration time
is directly proportional to the input signal (TRI). See
FIGURE 3-1:
Basic Dual Slope Converter.
In a simple dual slope converter, a complete
conversion requires the integrator output to “ramp-up”
and “ramp-down.” A simple mathematical equation
relates the input signal, reference voltage and
integration time.
EQUATION 3-1:
For a constant VIN:
EQUATION 3-2:
The dual slope converter accuracy is unrelated to the
integrating resistor and capacitor values as long as
they are stable during a measurement cycle. An
inherent benefit is noise immunity. Noise spikes are
integrated or averaged to zero during the integration
periods. Integrating ADCs are immune to the large
conversion
errors
that
plague
successive
approximation converters in high noise environments.
Interfering signals with frequency components at
multiples of the averaging period will be attenuated.
Integrating ADCs commonly operate with the signal
integration period set to a multiple of the 50/60Hz
power line period (see Figure 3-2).
FIGURE 3-2:
Normal Mode Rejection of
Dual Slope Converter.
+
–
REF
Voltage
Analog
Input
Signal
+
–
DISPLAY
Switch
Driver
Control
Logic
Int
egr
at
or
Output
Counter
Polarity Control
Phase
Control
VIN VREF
VIN 1/2 VREF
Variable
Reference
Integrate
Time
Fixed
Signal
Integrate
Time
Integrator
C
Comparator
+/–
Where:
VR
=
Reference voltage
TSI
=
Signal integration time (fixed)
TRI
=
Reference voltage integration time
(variable).
1
RC
--------
V
IN
0
T
SI
∫
t
()dt
V
RTRI
RC
---------------
=
VIN = VR
TRI
TSI
30
20
10
0
N
o
rm
a
lMode
Re
je
c
ti
on
(dB)
0.1/T
1/T
10/T
Input Frequency
T = Measured Period
Where:
FOSC
=
Clock Frequency at Pin 38
VFS
=
Full Scale Input Voltage
RINT
=
Integrating Resistor
VINT
=
Desired Full Scale Integrator Output
Swing
C
INT
4000
()
1
F
OSC
-------------
VFS
R
INT
-----------
V
INT
------------------------------------------------------
=
相關PDF資料
PDF描述
TC7107CPL 1-CH DUAL-SLOPE ADC, PARALLEL ACCESS, PDIP40
TC7107ACLW713 1-CH DUAL-SLOPE ADC, PARALLEL ACCESS, PQCC44
TC7107CLW713 1-CH DUAL-SLOPE ADC, PARALLEL ACCESS, PQCC44
TC7107IPL 1-CH DUAL-SLOPE ADC, PARALLEL ACCESS, PDIP40
TC7107AIPLG 1-CH DUAL-SLOPE ADC, PARALLEL ACCESS, PDIP40
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