參數(shù)資料
型號(hào): TC7109ACLW
廠商: TelCom Semiconductor, Inc.
英文描述: 12-BIT UP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS
中文描述: 12位向上兼容的模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 7/21頁
文件大?。?/td> 274K
代理商: TC7109ACLW
3-97
TELCOM SEMICONDUCTOR, INC.
7
6
5
4
3
1
2
8
Figure 2. TC7109A Parallel Interface With 8048/8049 Microcomputer
40
1
17
V
GND
TEST
RUN/HOLD
STATUS
LBEN
HBEN
39
38
37
36
35
34
33
32
31
30
29
28
27
25
24
23
22
21
TC7109A
1
4
5
6
7
8
9
11
25
26
39
40
20
TO
RESET
SS
INT
EA
WR
PSEN
ALE
PROG
V
TL
V
GND
P20–P27
2
8748/8049
CMOS
MICROCOMPUTER
+5V
OTHER I/O
+5V
GND
–5V
GND
3.58MHz
CRYSTAL
ANALOG
GND
EXTERNAL
REFERNCE
+
+
INPUT
C
0.33
μ
F
AZ
RINT
20k
10 k
0.2 V
1 V
XTAL2
XTALI
8
5
P14–P17
P13
P12
P11
P10
DB0–DB7
RD
30
29
28
27
B9–B12,
POL, OR
B1–B8
CE/LOAD
21–24,
35–38
12–19
10
31–34
26
2
18
19
C
0.15
μ
F
INT
0.01
μ
F
1M
1
μ
F
GND
+5V
+5V
+5V
+5V
GND
DD
CC
2
3
6
8
3–8
9–16
20
REF IN–
REF CAP–
REF CAP+
REF IN+
IN HI
HI LO
COM
INT
AZ
BUFF
REF OUT
V
OSC SEL
OSC OUT
OSC IN
MODE
SEND
BUFF OSC OUT
8
+
REF
REF
Signal-Integrate Phase
The buffer and integrator inputs are removed from
common and connected to input high and input low. The
auto-zero loop is opened. The auto-zero capacitor is placed
in series in the loop to provide an equal and opposite
compensating offset voltage. The differential voltage be-
tween input high and input low is integrated for a fixed time
of 2048 clock periods. At the end of this phase, the polarity
of the integrated signal is determined. If the input signal has
no return to the converter's power supply, input low can be
tied to analog common to establish the correct common-
mode voltage.
Deintegrate Phase
Input high is connected across the previously-charged
reference capacitor and input low is internally connected to
analog common. Circuitry within the chip ensures the ca-
pacitor will be connected with the correct polarity to cause
the integrator output to return to the zero crossing (estab-
lished by auto-zero) with a fixed slope. The time, repre-
sented by the number of clock periods counted for the output
to return to zero, is proportional to the input signal.
DETAILED DESCRIPTION
(All Pin Designations Refer to 40-Pin DIP)
Analog Section
The functional diagram shows a block diagram of the
analog section of the TC7109A. The circuit will perform
conversions at a rate determined by the clock frequency
(8192 clock periods per cycle), when the RUN/HOLD input
is left open or connected to V
+
. Each measurement cycle is
divided into four phases, as shown in Figure 3. They are:
(1) Auto-Zero (AZ), (2) Signal Integrate (INT), (3) Reference
Deintegrate (DE), and (4) Zero Integrator (ZI).
Auto-Zero Phase
The buffer and the integrator inputs are disconnected
from input high and input low and connected to analog
common. The reference capacitor is charged to the refer-
ence voltage. A feedback loop is closed around the system
to charge the auto-zero capacitor, C
AZ
, to compensate for
offset voltage in the buffer amplifier, integrator, and com-
parator. Since the comparator is included in the loop, the AZ
accuracy is limited only by the noise of the system. The offset
referred to the input is less than 10
μ
V.
TC7109
TC7109A
12-BIT
μ
P-COMPATIBLE
ANALOG-TO-DIGITAL CONVERTERS
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