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參數(shù)資料
| 型號(hào)： | TC7117ACLWTR |
| 元件分類： | ADC |
| 英文描述： | 1-CH 22-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 410K |
| 代理商： | TC7117ACLWTR |
2006 Microchip Technology Inc.
DS21457C-page 11
TC7116/A/TC7117/A
3.2.1
SYSTEM TIMING
The clocking method used for the TC7116/TC7116A
and TC7117/TC7117A is shown in Figure . Three
clocking methods may be used:
1.
An external oscillator connected to Pin 40.
2.
A crystal between Pins 39 and 40.
3.
An RC network using all three pins.
The oscillator frequency is
÷4 before it clocks the
decade counters. It is then further divided to form the
three convert cycle phases: Signal Integrate (1000
counts), Reference De-integrate (0 to 2000 counts),
and Auto-Zero (1000 to 3000 counts). For signals less
than full scale, auto-zero gets the unused portion of ref-
erence de-integrate. This makes a complete measure
cycle of 4000 (16,000 clock pulses), independent of
input voltage. For 3 readings per second, an oscillator
frequency of 48kHz would be used.
To achieve maximum rejection of 60Hz pickup, the sig-
nal integrate cycle should be a multiple of 60Hz. Oscil-
lator frequencies of 240kHz, 120kHz, 80kHz, 60kHz,
48kHz, 40kHz, etc. should be selected. For 50Hz rejec-
tion,
oscillator
frequencies
of
200kHz,
100kHz,
66-2/3kHz, 50kHz, 40kHz, etc. would be suitable. Note
that 40kHz (2.5 readings per second) will reject both
50Hz and 60Hz.
3.2.2
HOLD READING INPUT
When HLDR is at a logic HIGH, the latch will not be
updated. Analog-to-Digital conversions will continue,
but will not be updated until HLDR is returned to LOW.
To continuously update the display, connect to TEST
(TC7116/TC7116A) or GROUND (TC7117/TC7117A),
or disconnect. This input is CMOS compatible with
70k
Ω typical resistance to TEST (TC7116/TC7116A) or
GROUND (TC7117/TC7117A).
FIGURE 3-6:
TC7117/TC7117A Digital Section
TC7117
TC7117A
4
39
OSC2
V+
Digital
GND
TEST
35
Clock
40
38
OSC3
OSC1
÷
HLDR
Control Logic
Typical Segment Output
Digital Ground
To
Segment
V+
0.5mA
8mA
37
21
500
Ω
V+
1
Latch
~70k
Ω
To Switch Drivers
From Comparator Output
Internal Digital Ground
Thousands
Hundreds
Tens
Units
7-Segment
Decode
7-Segment
Decode
7-Segment
Decode
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