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參數(shù)資料
| 型號(hào)： | TC7126IPL |
| 元件分類： | ADC |
| 英文描述： | 1-CH DUAL-SLOPE ADC, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 21/22頁 |
| 文件大?。?/td> | 554K |
| 代理商： | TC7126IPL |
TC7126/A
DS21458B-page 8
2002 Microchip Technology Inc.
34
(7)
CREF+A 0.1F capacitor is used in most applications. If a large Common mode voltage
exists (for example, the VIN- pin is not at analog common) and a 200mV scale is
used, a 1
F capacitor is recommended and will hold the rollover error to 0.5 count.
35
(6)
VREF-
See Pin 36.
36
(5)
VREF+
The analog input required to generate a full scale output (1999 counts). Place 100mV
between Pins 35 and 36 for 199.9mV full scale. Place 1V between Pins 35 and 36 for
2V full scale. See Section 6.6, Reference Voltage for additional information.
37
(4)
TEST
Lamp test. When pulled HIGH (to V+), all segments will be turned on and the display
should read -1888. It may also be used as a negative supply for externally
generated decimal points. See Section 7.4, TEST for additional information.
38
(3)
OSC3
See Pin 40.
39
(2)
OSC2
See Pin 40.
40
(1)
OSC1
Pins 40, 39 and 38 make up the oscillator section. For a 48kHz clock (3 readings,
39 per second), connect Pin 40 to the junction of a 180k
resistor and a 50pF
capacitor. The 180k
resistor is tied to Pin 39 and the 50pF capacitor is tied to
Pin 38.
TABLE 2-1:
PIN FUNCTION TABLE (CONTINUED)
Pin Number
(40-Pin PDIP)
Normal
(Reversed)
Symbol
Description
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