TC7129
DS21459D-page 8
2006 Microchip Technology Inc.
Figure 3-1:
Standard Circuit.
3.3
Integrating Capacitor (CINT)
The charge stored in the integrating capacitor during
the integrate phase is directly proportional to the input
voltage. The primary selection criterion for CINT is to
choose a value that gives the highest voltage swing
while remaining within the high-linearity portion of the
integrator output range. An integrator swing of 2V is the
recommended value. The capacitor value can be
calculated using the following equation:
EQUATION 3-1:
Using the values derived above (assuming 60 Hz
operation), the equation becomes:
EQUATION 3-2:
The capacitor should have low dielectric absorption to
ensure good integration linearity. Polypropylene and
Teflon capacitors are usually suitable. A good
measurement of the dielectric absorption is to connect
the
reference
capacitor
across
the
inputs
by
connecting:
Pin-to-Pin:
20
→ 33 (CREF+ to IN HI)
30
→ 32 (CREF– to IN LO)
A reading between 10,000 and 9998 is acceptable;
anything lower indicates unacceptably high dielectric
absorption.
3.4
Reference Capacitor (CREF)
The reference capacitor stores the reference voltage
during several phases of the measurement cycle. Low
leakage is the primary selection criterion for this com-
ponent. The value must be high enough to offset the
effect of stray capacitance at the capacitor terminals. A
value of at least 1
μF is recommended.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
9V
+
Low Battery
Continuity
V+
5 pF
120
kHz
10 pF
0.1 F
20
k
Ω
0.1
F
100 k
Ω
CINT
0.1 F
V+
VIN
–
+
330 k
Ω
Crystal
RO
CO2
CRF
DREF
RREF
CIF
RIF
CREF+
1 F
10 k
Ω
RBIAS
150 k
Ω
RINT
OSC1
OSC3
ANNUNC
V
DISP
DP
4
/OR
Display Drive Outputs
DP
3
/UR
LATCH/
HOLD
V–
V+
INT
IN
INT
OUT
CONTINUITY
COMMON
C
REF
+
C
REF
–
BUFF
IN
LO
IN
HI
REF
HI
REF
LO
DGND
RANGE
DP
2
DP
1
OSC2
TC7129
CO1
CINT =
tINT x IINT
VSWING
Where tINT is the integration time.
CINT =
= 0.1
μA
16.7 msec x 13.3
μA
2V