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參數(shù)資料
| 型號(hào)： | TC7129IPL |
| 元件分類： | ADC |
| 英文描述： | 1-CH DUAL-SLOPE ADC, PDIP40 |
| 封裝： | 0.600 INCH, MO-011, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 7/28頁 |
| 文件大?。?/td> | 544K |
| 代理商： | TC7129IPL |
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2006 Microchip Technology Inc.
DS21459D-page 15
TC7129
4.11
Integrator Section
The integrator section includes the integrator, compar-
ator, input buffer amplifier and analog switches (see
Table 4-2) used to change the circuit configuration
during the separate measurement phases described
earlier. (See Figure 4-12).
The buffer amplifier has a common mode input voltage
range from 1.5V above V– to 1V below V+. The integra-
tor amplifier can swing to within 0.3V of the rails.
However, for best linearity, the swing is usually limited
to within 1V. Both amplifiers can supply up to 80
μA of
output current, but should be limited to 20
μA for good
linearity.
4.12
Continuity Indicator
A comparator with a 200 mV threshold is connected
between IN HI (pin 33) and IN LO (pin 32). Whenever
the voltage between inputs is less than 200 mV, the
CONTINUITY output (pin 27) will be pulled high,
activating the continuity annunciator on the display.
The continuity pin can also be used as an input to drive
the continuity annunciator directly from an external
source (see Figure 4-13).
A schematic of the input/output nature of this pin is also
shown in Figure 4-14.
Figure 4-13:
Continuity Indicator Circuit.
Figure 4-14:
Input/Output Pin Schematic.
4.13
Common and Digital Ground
The common and digital ground (DGND) outputs are
generated from internal Zener diodes. The voltage
between V+ and DGND is the internal supply voltage
for the digital section of the TC7129. Common can
source approximately 12
μA; DGND has essentially no
source capability (see Figure 4-15).
TABLE 4-2:
SWITCH LEGENDS
Label
Description
Label
Meaning.
DE
Open during all de-integrate phases.
DE–
Closed during all de-integrate phases when
input voltage is negative.
DE+
Closed during all de-integrate phases when
input voltage is positive.
INT1
Closed during the first integrate phase
(measurement of the input voltage).
INT2
Closed during the second integrate phase
(measurement of the amplifier offset).
INT
Open during both integrate phases.
REST
Closed during the rest phase.
ZI
Closed during the zero integrate phase.
X10
Closed during the X10 phase.
X10
Open during the X10 phase.
COM
Buffer
200 mV
IN HI
–
+
IN LO
–
+
V
CONT
500 k
Ω
To Display Driver
(Not Latched)
TC7129
500 k
Ω
DP4/OR, Pin 20
DP3/UR, Pin 21
LATCH/HOLD Pin 22
CONTINUITY, Pin 27
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