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參數(shù)資料
| 型號： | TC7MET540AFK |
| 廠商： | Toshiba Corporation |
| 英文描述： | TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic |
| 中文描述： | 東芝的CMOS數(shù)字集成電路硅單片 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大小： | 142K |
| 代理商： | TC7MET540AFK |
TC7MET540,541AFK
2001-10-23
4
Electrical Characteristics
DC Characteristics
Ta 25°C
Ta 40~85°C
Characteristics
Symbol
Test Condition
V
CC
(V)
Min
Typ.
Max
Min
Max
Unit
High level
V
IH
4.5~5.5
2.0
2.0
Input voltage
low level
V
IL
4.5~5.5
0.8
0.8
V
I
OH
50 A
4.5
4.4
4.5
4.4
High level
V
OH
V
IN
V
IH
or V
IL
I
OH
8 mA
4.5
3.94
3.80
I
OL
50 A
4.5
0
0.1
0.1
Output voltage
low level
V
OL
V
IN
V
IH
or V
IL
I
OL
8 mA
4.5
0.36
0.44
V
3-state output off-state current
I
OZ
V
IN
V
IH
or V
IL
V
OUT
V
CC
or GND
5.5
0.25
2.50
A
Input leakage current
I
IN
V
IN
5.5 V or GND
0~5.5
0.1
1.0
A
I
CC
V
IN
V
CC
or GND
Per input: V
IN
3.4 V
5.5
4.0
40.0
A
Quiescent supply current
I
CCT
Other input: V
CC
or GND
5.5
1.35
1.50
mA
Output leakage current
I
OPD
V
OUT
5.5 V
0
0.5
5.0
A
AC Electrical Characteristics
(Input: t
r
t
f
3 ns)
Ta 25°C
Ta 40~85°C
Characteristics
Symbol
Test Condition
V
CC
(V)
C
L
(pF)
Min
Typ.
Max
Min
Max
Unit
15
5.4
7.4
1.0
8.5
Propagation delay time
(TC7MET540AFK)
t
pLH
t
pHL
5.0 0.5
50
5.9
8.4
1.0
9.5
ns
15
5.0
6.9
1.0
8.0
Propagation delay time
(TC7MET541AFK)
t
pLH
t
pHL
5.0 0.5
50
5.5
7.9
1.0
9.0
ns
15
8.3
11.3
1.0
13.0
3-state output enable time
t
pZL
t
pZH
R
L
1 k
5.0 0.5
50
8.8
12.3
1.0
14.0
ns
3-state output disable time
t
pLZ
t
pHZ
R
L
1 k
5.0 0.5
50
9.4
11.9
1.0
13.5
ns
Output to output skew
t
osLH
t
osHL
(Note6) 5.0 0.5
50
1.0
1.0
ns
Input capacitance
C
IN
C
OUT
4
10
10
pF
Output capacitance
9
pF
Power dissipation
capacitance
C
PD
(Note7)
19
pF
Note6: Parameter guaranteed by design.
t
osLH
|t
pLHm
t
pLHn
|, t
osHL
|t
pHLm
t
pHLn
|
Note7: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
I
CC (opr)
C
PD
V
CC
f
IN
I
CC
/8 (per bit)
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