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參數(shù)資料
| 型號： | TC7MPS3125FTG |
| 廠商： | Toshiba Corporation |
| 英文描述： | Low Voltage/Low Power 1 + 3-Bit Dual Supply Bus Transceiver |
| 中文描述： | 低電壓/低功率1 3位雙電源總線收發(fā)器 |
| 文件頁數(shù)： | 16/22頁 |
| 文件大?。?/td> | 311K |
| 代理商： | TC7MPS3125FTG |
TC7MPS3125FTG
2007-10-19
16
V
CCA
=
1.8
±
0.15 V, V
CCB
=
2.5
±
0.2 V
Characteristics
Symbol
Test Condition
Min
Max
Unit
Propagation delay time
(Bn
→
An)
t
pLH
t
pHL
Figure 1, Figure 2
1.0
9.1
3-state output enable time
(OE
→
An)
t
pZL
t
pZH
Figure 1, Figure 3
1.0
13.5
3-state output disable time
(
OE
→
An)
t
pLZ
t
pHZ
Figure 1, Figure 3
1.0
11.8
ns
Propagation delay time
(An
→
Bn)
t
pLH
t
pHL
Figure 1, Figure 2
1.0
9.5
3-state output enable time
(
OE
→
Bn)
t
pZL
t
pZH
Figure 1, Figure 3
1.0
12.6
3-state output disable time
(OE
→
Bn)
t
pLZ
t
pHZ
Figure 1, Figure 3
1.0
5.1
ns
Output to output skew
t
osLH
t
osHL
(Note)
0.5
ns
Note: Parameter guaranteed by design.
(t
osLH
=
|t
pLHm
t
pLHn
|, t
osHL
=
|t
pHLm
t
pHLn
|)
V
CCA
=
1.5
±
0.1 V, V
CCB
=
2.5
±
0.2 V
Characteristics
Symbol
Test Condition
Min
Max
Unit
Propagation delay time
(Bn
→
An)
t
pLH
t
pHL
Figure 1, Figure 2
1.0
10.8
3-state output enable time
(OE
→
An)
t
pZL
t
pZH
Figure 1, Figure 3
1.0
18.3
3-state output disable time
(OE
→
An)
t
pLZ
t
pHZ
Figure 1, Figure 3
1.0
14.2
ns
Propagation delay time
(An
→
Bn)
t
pLH
t
pHL
Figure 1, Figure 2
1.0
10.5
3-state output enable time
(OE
→
Bn)
t
pZL
t
pZH
Figure 1, Figure 3
1.0
15.4
3-state output disable time
(OE
→
Bn)
t
pLZ
t
pHZ
Figure 1, Figure 3
1.0
6.4
ns
Output to output skew
t
osLH
t
osHL
(Note)
1.5
ns
Note: Parameter guaranteed by design.
(t
osLH
=
|t
pLHm
t
pLHn
|, t
osHL
=
|t
pHLm
t
pHLn
|)
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