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參數(shù)資料
| 型號： | TC820C/LW |
| 元件分類： | ADC |
| 英文描述： | 1-CH 3-BIT DUAL-SLOPE ADC, PARALLEL ACCESS, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 13/34頁 |
| 文件大?。?/td> | 435K |
| 代理商： | TC820C/LW |
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TC820
DS21476C-page 20
2007 Microchip Technology Inc.
5.8
Ratiometric Resistance
Measurements
The TC820 true differential input and differential
reference make ratiometric readings possible. In ratio-
metric operation, an unknown resistance is measured
with respect to a known standard resistance. No
accurately defined reference voltage is needed.
The unknown resistance is put in series with a known
standard and a current is passed through the pair
(Figure 5-8). The voltage developed across the unknown
is applied to the input and voltages across the known
resistor applied to the reference input. If the unknown
equals the standard, the input voltage will equal the refer-
ence voltage and the display will read 2000. The displayed
reading can be determined from the following expression:
EQUATION 5-3:
The display will over range for values of RUNKNOWN
≥ 2x R
STANDARD.
FIGURE 5-8:
Low Parts Count
Ratiometric Resistance Measurement.
5.9
Buffering the FREQ Input
When the FREQ/VOLTS input is high and the LOGIC
input is low, the TC820 will count pulses at the RANGE/
FREQ input. The time-base will be FOSC/40,000, or
1 second with a 40kHz clock. The signal to be
measured should swing from VDD to DGND. The
RANGE/FREQ input has CMOS input levels without
hysteresis. For best results, especially with low
frequency sine-wave inputs, an external buffer with
hysteresis should be added. A typical circuit is shown
in Figure 5-9.
FIGURE 5-9:
Frequency Counter External
Buffer.
5.10
Logic Probe Inputs
The DP0/LO and DP1/HI inputs provide the logic probe
inputs when the LOGIC input is high. Driving either
DP0/LO or DP1/HI to a logic high will turn on the
appropriate LCD annunciator. When DP0/LO is high,
the buzzer will be on.
To provide a "single input" logic probe function, external
buffers should be used. A simple circuit is shown in
Figure 5-10. This circuit will turn the appropriate annun-
ciator on for high and low level inputs.
FIGURE 5-10:
Simple External Logic Probe
Buffer.
If carefully controlled logic thresholds are required, a
window comparator can be used. Figure 5-11 shows a
typical circuit. This circuit will turn on the high or low
annunciators when the logic thresholds are exceeded,
but the resistors connected from DP0/LO and DP1/HI
to DGND will turn both annunciators off when the logic
probe is unconnected.
The TC820 logic inputs are not latched internally, so
pulses of short duration will usually be difficult or
impossible to see. To display short pulses properly, the
input pulse should be "stretched." The circuit of
Figure 5-11 shows capacitors added across the input
pull-down resistors to stretch the input pulse and permit
viewing short duration input pulses.
Displayed Reading =
RUNKNOWN
RSTANDARD
TC820
RSTANDARD
RUNKNOWN
Analog
Common
VDD
VREF+
VREF-
VIN+
VIN-
LCD
TC820
+
DGND
Frequency
Input
GND
DGND
74HC14
RANGE/FREQ
FREQ/VOLTS
VDD
1F
+9V
VDD
TC820
Logic
Probe
Input
+9V
*74HC14
LOGIC
DP1/HI
DP0/LO
DGND
*
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