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參數(shù)資料
| 型號(hào)： | TC820CLWTR |
| 元件分類： | ADC |
| 英文描述： | 1-CH DUAL-SLOPE ADC, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 616K |
| 代理商： | TC820CLWTR |
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TC820
DS21476B-page 20
2002 Microchip Technology Inc.
FIGURE 5-8:
LOW PARTS COUNT
RATIOMETRIC
RESISTANCE
MEASUREMENT
5.9
Buffering the FREQ Input
When the FREQ/VOLTS input is high and the LOGIC
input is low, the TC820 will count pulses at the RANGE/
FREQ input. The time-base will be FOSC/40,000, or
1 second with a 40kHz clock. The signal to be mea-
sured should swing from VDD to DGND. The RANGE/
FREQ input has CMOS input levels without hysteresis.
For best results, especially with low frequency sine-
wave inputs, an external buffer with hysteresis should
be added. A typical circuit is shown in Figure 5-9.
FIGURE 5-9:
FREQUENCY COUNTER
EXTERNAL BUFFER
5.10
Logic Probe Inputs
The DP0/LO and DP1/HI inputs provide the logic probe
inputs when the LOGIC input is high. Driving either
DP0/LO or DP1/HI to a logic high will turn on the appro-
priate LCD annunciator. When DP0/LO is high, the
buzzer will be on.
To provide a "single input" logic probe function, external
buffers should be used. A simple circuit is shown in
Figure 5-10. This circuit will turn the appropriate annun-
ciator on for high and low level inputs.
FIGURE 5-10:
SIMPLE EXTERNAL
LOGIC PROBE BUFFER
If carefully controlled logic thresholds are required, a
window comparator can be used. Figure 5-11 shows a
typical circuit. This circuit will turn on the high or low
annunciators when the logic thresholds are exceeded,
but the resistors connected from DP0/LO and DP1/HI
to DGND will turn both annunciators off when the logic
probe is unconnected.
The TC820 logic inputs are not latched internally, so
pulses of short duration will usually be difficult or impos-
sible to see. To display short pulses properly, the input
pulse should be "stretched." The circuit of Figure 5-11
shows capacitors added across the input pull-down
resistors to stretch the input pulse and permit viewing
short duration input pulses.
FIGURE 5-11:
WINDOW COMPARATOR
LOGIC PROBE
TC820
RSTANDARD
RUNKNOWN
Analog
Common
VDD
VREF+
VREF-
VIN+
VIN-
LCD
TC820
+
DGND
Frequency
Input
GND
DGND
74HC14
RANGE/FREQ
FREQ/VOLTS
VDD
1F
+9V
VDD
TC820
Logic
Probe
Input
+9V
*74HC14
LOGIC
DP1/HI
DP0/LO
DGND
*
+
–
VDD
TC820
R1
DP1/HI
LOGIC
DP0/LO
DGND
1N4148
+9V
VL
R2
R3
1M
1M
Logic
Probe Input
Note: Select R1, R2, R3 for desired logic thresholds.
+
–
VH
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