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參數(shù)資料
| 型號： | TC820CPL |
| 元件分類： | ADC |
| 英文描述： | 1-CH DUAL-SLOPE ADC, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 23/24頁 |
| 文件大小： | 185K |
| 代理商： | TC820CPL |
8
3-3/4 A/D Converter with Frequency
Counter and Logic Probe
TC820
TC820-10 10/17/96
2001 Microchip Technology Inc.
DS21476A
GENERAL THEORY OF OPERATION
Dual-Slope Conversion Principles
The TC820 analog-to-digital converter operates on the
principle of dual-slope integration. An understanding of the
dual-slope conversion technique will aid the user in follow-
ing the detailed TC820 theory of operation following this
section. A conventional dual-slope converter measurement
cycle has two distinct phases:
(1) Input Signal Integration
(2) Reference Voltage Integration (Deintegration)
Referring to Figure 2, the unknown input signal to be
converted is integrated from zero for a fixed time period
(t INT), measured by counting clock pulses. A constant
reference voltage of the opposite polarity is then integrated
until the integrator output voltage returns to zero. The
reference integration (deintegration) time (TDEINT) is then
directly proportional to the unknown input voltage (VIN).
In a simple dual-slope converter, a complete conver-
sion requires the integrator output to "ramp-up" from zero
and "ramp-down" back to zero. A simple mathematical
equation relates the input signal, reference voltage, and
integration time:
9V
L-E4
AGD4
BC4P3
BC3P2
OFE2
AGD2
BC2P1
PK
FE1
AGD1
BC1BT
BP3
BP2
BP1
HFE3
AGD3
10 11 12 13 14 15
17
9
8
7
6
5
4
3
2
1
LOGIC HIGH
LOGIC LOW
OVERRANGE
PKHOLD
LOW BATT
FREQ/
VOLTS
LOGIC
DP0/LO
DP1/HI
DGND
NC
ANNUNC
COM
BUZ OUT
BUZ IN
PK HOLD
30
31
27
40
26
22
23
25
OSC1
OSC2 OSC3 VBUFF CAZ
VINT
VDD
VSS
V
+
REF
V
–
REF
TC820
C
+
REF C
–
REF
24
18
33
32
16
19
20
21
V
+
IN
V
–
IN
37
38
39
34
35
36
28
29
40kHz
470
k
NC
100
k
0.47
F
0.2
F
0.1
F
22M
NOTE:
Pin numbers are for
40-pin package.
PIEZO
BUZZER
DGND
VDD
1
F
+
VDD
22k
2k
VREF = 200mV
CHANGE
RANGE
TO
SWITCH
S1a
NO DP
S2
DP3
DP2
DP1
DGND
S1e
S1d
LOGIC
FREQ
GND
VIN
VDD
S1c
S1b
S1a
TO SWITCH
S2
100k
0.01
F
VDD
COM
RANGE/FREQ
+
–
+
–
REF
VOLTAGE
ANALOG
INPUT
SIGNAL
+
–
DISPLAY
SWITCH
DRIVER
CONTROL
LOGIC
INTEGRATOR
OUTPUT
CLOCK
COUNTER
POLARITY CONTROL
PHASE
CONTROL
VIN
VFULL SCALE
1.2 VFULL SCALE
VARIABLE
REFERENCE
INTEGRATE
TIME
FIXED
SIGNAL
INTEGRATE
TIME
INTEGRATOR
C
COMPARATOR
R
=
Figure 2. Basic Dual-Slope Converter
Figure 1. Typical Operating Circuit
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