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參數(shù)資料
| 型號： | TC90A58F |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 31/36頁 |
| 文件大?。?/td> | 439K |
| 代理商： | TC90A58F |
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TC90A58F
2002-02-06
4
Pin Functions
No.
Pin Name
I/O
Function
Notes
1
BIAS
O
Bias pin (for AD)
Ground to AVSS (pin 6) via 0.1-
F capacitor.
2
VRM_I
O
AD reference voltage (middle)
Same as above
3
VRB_I
O
AD reference voltage (bottom)
Same as above
4
AVDD
Analog power supply
5
AIN_I
I
AD input
Connect 0.47-
F capacitor and 20- resistor.
6
AVSS
Analog GND
7
VRT_I
O
AD reference voltage (top)
Ground to AVSS (pin 6) via 0.1-
F capacitor.
8
DACOUT
O
Analog pin (for testing)
For testing purposes
9
VB1
Analog pin (for testing)
Ground to AVSS (pin 14) via 0.1-
F capacitor.
10
VRM_Q
O
AD reference voltage (middle)
Ground to AVSS (pin 14) via 0.1-
F capacitor.
11
VRB_Q
O
AD reference voltage (bottom)
Ground to AVSS (pin 14) via 0.1-
F capacitor.
12
AVDD
Analog power supply
13
AIN_Q
I
AD input
Connect 0.47-
F capacitor and 20- resistor.
14
AVSS
Analog GND
15
VRT_Q
O
AD reference voltage (top)
Ground to AVSS (pin 14) via 0.1-
F capacitor.
16
PVDD
HPLL power supply
17
APCLK
O
Clock output
Outputs clock with amplitude of 1 Vp-p according to
corresponding I
2C bus register setting.
When I
2
C bus register settings are default values, outputs are
fixed to L.
18
PVSS
HPLL GND
19
LFIL
HPLL filter
Connecta 1-
F capacitor and a 1.0-k resistor.
Connect other end of capacitor as near to PVSS as possible.
Also connect 0.01-
F capacitor in parallel with above capacitor
and resistor.
20
BFIL
For stabilization
Connect 0.01-
F capacitor.
21
DVDDP
Digital power supply
For HPLL
22
EXTCLK
I
External clock input
Used as clock input pin in External Clock Mode.
When built-in HPLL is used, set input to H or fix input to L.
23
DVSSP
Digital GND
For HPLL
24
HDIN
I
HD input
5-V withstanding voltage
25
VDIN
I
VD input
5-V withstanding voltage
26
HREF
I
HPLL pin
Input for external HPLL reference signal
Phase is compared on rising edge.
27
SDA
I/O
I
2
C bus data
5-V withstanding voltage
28
SCL
I
2
C bus clock
5-V withstanding voltage
29
VDOUT
O
VD output
Outputs vertical sync signal pulse.
Pulse polarity can be set using I
2
C bus register.
30
HDOUT
O
HD output
Outputs horizontal sync signal pulse.
Pulse polarity can be set using I
2
C bus register.
31
DVDD
Digital power supply
Internal, for output PAD
32
DVSS
Digital GND
Internal, for output PAD
33
BOUT0
O
-/B/-OUTPUT
34
BOUT1
O
-/B/-OUTPUT
35
BOUT2
O
-/B/-OUTPUT
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