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參數(shù)資料
| 型號(hào)： | TC9205M-DS-R03 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Crimp; Body Material:Aluminum; Series:PT06; No. of Contacts:3; Connector Shell Size:8; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight |
| 中文描述： | 5端口10/100/1000智能以太網(wǎng)交換機(jī) |
| 文件頁數(shù)： | 12/51頁 |
| 文件大?。?/td> | 1661K |
| 代理商： | TC9205M-DS-R03 |
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TC9205M
Preliminary Data Sheet
Pin Listing
(continued)
No.
P19
Pin label
TxData4_4
FcBcstEn
Type
I/O
pd
Description
GMII transmit data - bit 4
Enables/disables flow control for broadcast packets.
'1' – enabled
'0' – disabled
FcBcstEn is latched on reset.
I/O
pd
GMII/MII transmit data - bit 3
G
Digital ground for core
I/O
pd
GMII/MII transmit data - bit 2
GMII/MII transmit data - bit 1
I/O
pd
Priority class - most significant bit.
PriClass[4] is latched on reset.
GMII/MII transmit data - least significant bit
I/O
pu
Priority class - least significant bit. Sets priority level per port basis.
PriClass[4] - '00' - port 4 low priority
PriClass[4] - '01' - port 4 has normal priority
PriClass[4] - '10' - port 4 has high priority
PriClass[4] - '11' - port 4 has very high priority
PriClass[4] is latched on reset
GMII/MII transmit enable
I/O
pd
If this pin is set to '1' then all frames with 802.1D Reserved Group
Address or 802.3x Full Duplex PAUSE operation DA will be filtered
out. This setting is provided for testing purposes only and it is
recommended to set high in normal operation.
RejRDA is latched on reset.
O
GMII transmit clock
P
Digital +3.3V power supply for I/O
I/O
pd
Transmit Error
I
MII transmit clock
I
s
MII carrier sense indication
I
s
MII collision indication
I
s
Receive Error
G
Digital ground for I/O
I
MII receive clock
I
s
GMII/MII data valid
I
s
GMII receive data - least significant nibble.
MII receive data
I
s
GMII receive data - least significant nibble.
MII receive data
I
s
GMII receive data - least significant nibble.
MII receive data
I
s
GMII receive data - least significant nibble.
MII receive data
I
s
GMII receive data - most significant nibble
I
s
GMII receive data - most significant nibble
P18 TxData4_3
D17 Vss 2.0
R20 TxData4_2
TxData4_1
R19
PriClass4_1
TxData4_0
PriClass4_0
R18
TxEn4
RejRDA
M18
T19 GTxClk4
D7
Vdd 3.3
N20 TxEr4
T20 TxClk4
V19 Crs4
V18 Col4
U20 RxEr4
D11 Vss 3.3
T17 RxClk4
T18 RxDv4
W19 RxData4_0
Y19 RxData4_1
Y20 RxData4_2
W20 RxData4_3
V20 RxData4_4
U17 RxData4_5
Confidential.
Copyright
2003, IC Plus Corp.
12/51
July 30, 2003
TC9205M-DS-R03
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