參數(shù)資料
型號: TC9447F
廠商: Toshiba Corporation
元件分類: 數(shù)字信號處理
英文描述: Single-Chip Audio Digital Signal Processor
中文描述: 單芯片音頻數(shù)字信號處理器
文件頁數(shù): 40/44頁
文件大小: 635K
代理商: TC9447F
TC9447F
2002-02-05
40
Microcontroller Interface
Standard transmission mode
(CS, IFCK, IFDI, IFDO,
ACK
)
Characteristics
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
Standby time
t
STB
1.0
μs
CS
- IFCK
Setup time (Mode 1)
t
CCD
0.5
μs
IFCK “L” cycle width
t
WLC
0.5
μs
IFCK “H” cycle width
t
WHC
0.5
μs
IFCK
-
CS
Setup time
t
CKC
0.5
μs
CS
“H” cycle width
t
WCS
(Note 13)
1.0
μs
IFCK
-
CS
Setup time (Mode 2)
t
CCU
0.5
μs
IFCK
-
CS
Setup time
t
SCK
0.5
μs
IFDI - IFCK
Setup time
t
SCD
0.5
μs
IFCK
- IFDI
Hold time
t
HCD
0.5
μs
IFCK
- IFDO
Propagation delay time
t
DDO
C
L
= 30 pF
0.5
μs
IFCK
-
ACK
Propagation delay time
t
DAKD
C
L
= 30 pF
(Pull-up resistor) R
L
= 1 k
0.5
μs
IFCK
-
ACK
Propagation delay time
t
DAKZ
C
L
= 30 pF
(Pull-up resistor) R
L
= 1 K
0.5
μs
Note 13: The command which is "Sync" in the transfer Sync with Sync signal of a 17 page table 1 control command
table needs to set the
CS
= H section to a minimum of 1 fs more until it transmits the following command.(It
needs more than 22.68 μs at fs = 44.1 kHz)
I
2
C mode
(CS, IFCK, IFDI)
Characteristics
Symbol
Test
Circuit
Test Condition
Min
Typ.
Max
Unit
IFCK clock frequency
f
IFCK
C
L
= 400 pF
0
400
kHz
IFCK “H” cycle width
t
H
C
L
= 400 pF
0.6
μs
IFCK “L” cycle width
t
L
C
L
= 400 pF
1.3
μs
Data setup time
t
DS
C
L
= 400 pF
0.1
μs
Data hold time
t
DH
C
L
= 400 pF
0
μs
Transmission start condition hold
time
t
SCH
C
L
= 400 pF
0.6
μs
Repeat transmission start
condition setup time
t
SCS
C
L
= 400 pF
0.6
μs
Transmission end condition setup
time
t
ECS
C
L
= 400 pF
0.6
μs
Data transmission interval
I
2
C rise time
I
2
C fall time
t
BUF
C
L
= 400 pF
1.3
μs
t
R
C
L
= 400 pF
0.3
μs
t
F
C
L
= 400 pF
0.3
μs
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