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參數(shù)資料
| 型號： | TDA10021HT |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | DVB-C channel receiver |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, PLASTIC, MS-026, SOT-357-1, TQFP-64 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 92K |
| 代理商： | TDA10021HT |
2001 Oct 01
5
Philips Semiconductors
Product specification
DVB-C channel receiver
TDA10021HT
SCLT
20
OD
SCLT can be configured to be a control line output or to output the SCL input. This
is controlled by parameter BYPIIC and CTRL_SCLT of register TEST (index 0F).
SCLT is an open-drain output and therefore requires an external pull-up resistor.
when HIGH this pin enables the serial output transport stream through the
boundary scan pins TRST, TDO, TCK, TDI and TMS (serial interface). Must be set
LOW in bist and boundary scan mode.
test clock: an independent clock used to drive the TAP controller in boundary scan
mode. In normal mode of operation, TCK must be set LOW. In serial stream mode,
TCK is the clock output (OCLK).
test data input: the serial input for test data and instruction in boundary scan mode.
In normal mode of operation, TDI must be set LOW. In serial stream mode, the TDI
is the PSYNC output.
digital supply voltage for the core (1.8 V typ.)
digital ground for the core
test reset: this active LOW input signal is used to reset the TAP controller in
boundary scan mode. In normal mode of operation, TRST must be set LOW. In
serial stream mode, TRST is the uncorrectable output (UNCOR).
test mode select: this input signal provides the logic levels needed to change the
TAP controller from state to state. In normal mode of operation, TMS must be set to
HIGH. In serial stream mode, TMS is the DEN output.
test data output: this is the serial test output pin used in boundary scan mode.
Serial data is provided on the falling edge of TCK. In serial stream mode, TDO is
the data output (DO).
GPIO can be configured by the I
2
C-bus either as:
A Front-End Lock indicator (FEL) (default mode)
An active LOW output interrupt line (IT) which can be configured by the I
2
C-bus
interface
A control output pin programmable by I
2
C-bus.
GPIO is an open-drain output and therefore requires an external pull-up resistor.
digital supply voltage for the pads (3.3 V typ.)
digital ground for the pads
CTRL is a control output pin programmable by the I
2
C-bus. CTRL is an open-drain
output and therefore requires an external pull-up resistor.
uncorrectable packet: this output signal is HIGH when the provided packet is
uncorrectable (during the 188 bytes of the packet). The uncorrectable packet is not
affected by the Reed Solomon decoder, but the MSB of the byte following the sync
byte is forced to logic 1 for the MPEG-2 process: error flag indicator (if RSI and IEI
are set LOW in the I
2
C-bus table).
pulse synchro: this output signal goes HIGH when the sync byte (0x47) is provided,
then it goes LOW until the next sync byte
output clock: this is the output clock for the DO[7:0] data outputs. OCLK is internally
generated depending on which interface is selected.
data enable: this output signal is HIGH when there is valid data on the output bus
DO[7:0]
ENSERI
21
I
TCK
22
I/O
TDI
23
I/O
V
DDDI8
V
SSDI8
TRST
24
25
26
S
G
I/O
TMS
27
I/O
TDO
28
O
GPIO
29
OD
V
DDD33
V
SSD33
CTRL
30
31
32
S
G
OD
UNCOR
33
O
PSYNC
34
O
OCLK
35
O
DEN
36
O
SYMBOL
PIN
TYPE
(1)
DESCRIPTION
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