參數(shù)資料
型號: TDA19989AET
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: 150 MHz pixel rate HDMI 1.4 transmitter with 3 x 8-bit video inputs, HDCP and CEC support
中文描述: SPECIALTY CONSUMER CIRCUIT, PBGA64
封裝: 4.50 X 4.50 MM, 0.95 MM HEIGHT, PLASTIC, SOT-962-3, TFBGA-64
文件頁數(shù): 5/8頁
文件大?。?/td> 61K
代理商: TDA19989AET
AN10920_1
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Application note
Rev. 01 — 19 April 2010
5 of 8
NXP Semiconductors
AN10920
Using CEC with TDA19989
3.1 Writing to the CEC data registers
All CEC data write operations must start by addressing the first CEC data register CDR[0]
at address 07h. CDR[0] indicates the number of CEC register bytes that are to be written
to accommodate the complete message. These bytes are written contiguously.
The minimum CEC message length allowed is 3 CEC register bytes. Any message
specifying less than 3 CEC register bytes is invalid.
If the number of CEC data registers actually written is less than the number indicated by
CDR[0], the message is ignored and no acknowledge message is sent.
If the number of CEC data registers written is greater than the number indicated in
CDR[0], the message is processed when the write to the last CEC data register specified
in CDR[0] has completed. The extra message bytes are ignored.
If the message length indicated in CDR[0] exceeds the maximum number of CEC data
registers available, the message is processed when the write to the last CEC data register
has completed. The extra message bytes are ignored.
3.2 Reading the CEC data registers
All CEC data read operations must start by addressing the first CEC data register CDR[0]
at address 07h. CDR[0] indicates the number of CEC register bytes that are to be read.
These bytes will be read contiguously.
When the CEC data registers contain a valid message, line INT is set and the Status
register INT bit is set to logic 1.
If the CEC data registers are read when line INT is not set, the value in CDR[0] is 0 which
indicates there are no bytes to be read. Any further attempts to read before a STOP
condition returns the value 00h.
If the host performs a write operation and then starts a read operation before resetting the
Address Pointer register, the read operation starts automatically from CDR[0].
If the read operation stops before all of the specified CEC data registers are read, line INT
is reset, the message is discarded and can never be read.
If the number of read CEC data registers is greater than the number indicated in the first
CEC data register, the read value is 00h. Line INT is reset when the last valid CEC data
register of the current message has been read.
S = START bit.
A = Acknowledge bit.
P = STOP bit.
Fig 2.
TDA19989 CEC data register write example
001aal814
68h
07h
06h
00h
4Fh
82h
20h
00h
S
A
A
A
A
A
A
A
P
CDR[0]
first byte message
write location
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