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參數(shù)資料
| 型號： | TDA4504B |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Small signal combination for multistandard colour TV |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP32 |
| 封裝： | PLASTIC, SOT-201, DIP-32 |
| 文件頁數(shù)： | 9/26頁 |
| 文件大小： | 190K |
| 代理商： | TDA4504B |
February 1992
9
Philips Semiconductors
Product specification
Small signal combination for multistandard colour TV
TDA4504B
Horizontal synchronization
The horizontal synchronization circuit
of the TDA4504B has been designed
as follows:
The retrace of the horizontal
oscillator occurs during the
horizontal retrace and not during
the scan period. This has the
advantage that no interference will
be visible on the screen when
receiving weak input signals. Video
crosstalk will not disturb the phase
of the horizontal locking.
Reduced frequency shift of the
horizontal oscillator due to noise
since the horizontal phase detector
reference signal is more
symmetrical and independent of
the supply voltage and
temperature.
The phase detector current ratio for
strong and weak signals is
increased to obtain a better
performance during both VCR
playback and weak signal
reception. The switching level is
also independent of temperature
and supply voltage.
Vertical synchronization
Generation of the vertical sawtooth
(pin 3) is accomplished by a divider
that permits the production of a
vertical frequency of either 50 Hz or
60 Hz with freedom from adjustment,
amplitude correction and maximum
interference/disturbance protection.
A discriminator window checks the
vertical trigger pulse. When the
trigger pulse occurs before count 576,
the divider system operates in the
60 Hz mode otherwise the 50 Hz
mode is selected. (2 clock pulses
equal one horizontal line).
The divider section operates with
different reset windows. These
windows are activated via an up/down
counter. This increases its count by 1
for each occasion the separated
vertical sync pulse is within the
selected window. On each occasion
the vertical sync. pulse is not within
the selected window, the count is
reduced by 1.
L
ARGE
(
SEARCH
)
WINDOW
;
DIVIDER
RATIO BETWEEN
488 - 722
This mode is valid for the following
conditions:
1
divider locking to another
transmitter
divider ratio found, not within
the narrow window limits
up/down counter value of the
divider system operating in
narrow window mode, count
falls below 10.
2
3
N
ARROW WINDOW
;
DIVIDER RATIO
BETWEEN
522 - 528 (60 H
Z
)
OR
622 -
628 (50 H
Z
)
The divider switches to this mode
when the up/down counter has
reached its maximum value of 15
approved vertical sync pulses. When
the divider operates in this mode and
a vertical sync pulse is missing within
the window, the divider is reset at the
end of the window and the count
lowered by 1. At a counter value
below 10, the divider switches to the
large window mode.
An anti-top flutter pulse is also
generated by the divider system. This
inhibits the horizontal phase-1
detector during the vertical sync
pulse. The width of this pulse
depends upon the divider mode. For
the large window mode the start is
generated at the divider reset. In the
narrow window mode the anti-top
flutter pulse starts at the beginning of
the first equalizing pulse. The anti-top
flutter pulse ends at count 10 for 50
Hz and count 12 for 60 Hz.
When out-of-sync is detected by the
coincidence detector, the divider is
switched to count 625. This results in
a stable vertical amplitude when no
input signal is available.
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