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參數(shù)資料
| 型號： | TDA4671 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Picture Signal Improvement PSI circuit |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP18 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 152K |
| 代理商： | TDA4671 |
1996 Dec 11
8
Philips Semiconductors
Product specification
Picture Signal Improvement (PSI) circuit
TDA4671
Colour-difference paths measured with transient times t
r
= t
f
= 1
μ
s; t
p H
≥
1
μ
s; V
i
= 1.33 V (p-p) on
pins 3 and 7 and with burst key pulse t
BK
= 4
μ
s
±
(R
Y) input signal
(peak-to-peak value; pin 3)
±
(B
Y) input signal
(peak-to-peak value; pin 7)
input transient sensitivity
V
3,7
internal clamping voltage level
I
3,7
input current
V
i(CD)(p-p)
75% colour bar
1.05
1.48
V
75% colour bar
1.33
1.88
V
V
3,7
/
δ
t
0.22
±
100
2.45
6
2
±
1
±
190
12
±
5
±
18
±
30
V/
μ
s
V
μ
A
μ
A
pF
V
mV
mV
mV
outside clamping
during clamping
C
3,7
V
4,6
V
4,6
input capacitance
DC output voltage
output offset voltage
R
S
≤
300
; note 1
during and after storage time
R
S
≤
300
; note 1
V
spike
spurious spike signals on pins 4
and 6
output current (emitter-follower with
constant current source)
I
4,6
source current
sink current
1
0.4
1
0
0
100
+1
±
0.3
mA
mA
dB
dB
R
4,6
G
v
G
v
LIN
output resistance
signal gain in each path
gain difference
(R
Y)/
(B
Y)
signal linearity for
nominal signal
+3 dB signal
signal reduction at higher frequency
(output signal ratio V
i
/V
o
)
V
o
/V
i
α
min
/
α
max
;
V
i
= 1.33 V (p-p)
V
i
= 1.88 V (p-p)
signal with t
p H
= 50 ns;
t
r
= t
f
= 1
μ
s
0.90
0.65
1.5
dB
V
o
Sandcastle pulse, input voltage selectable via I
2
C-bus
V
17
input voltage threshold for H and V
sync
input voltage threshold for burst
input voltage threshold for H and V
sync
input voltage threshold for burst
input resistance
SC5-bit = 0 (12 V)
1.1
1.5
1.9
V
SC5-bit = 0 (12 V)
SC5-bit = 1 (5 V)
5.5
1.1
6.5
1.5
7.5
1.9
V
V
SC5-bit = 1 (5 V)
+12 V input level
+5 V input level
3.0
30
15
3.0
3.5
40
20
4
4.0
1
4.0
50
25
8
4.6
V
k
k
pF
μ
s
μ
s
R
17
C
17
t
BK
t
d
input capacitance
burst key pulse width
leading edge delay for clamping
pulse
number of required burst key pulses
vertical blanking interval
referred to t
BK
n
p
note 2
4
31
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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