參數(shù)資料
型號(hào)： TDA4681WP
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 消費(fèi)家電
英文描述： Video processor with automatic cut-off and white level control
中文描述： SPECIALTY CONSUMER CIRCUIT, PQCC28
封裝： PLASTIC, SOT-261-2, LCC-28
文件頁(yè)數(shù)： 6/28頁(yè)
文件大小： 160K
代理商： TDA4681WP
1997 Mar 04
6
Philips Semiconductors
Product specification
Video processor with automatic cut-off
and white level control
TDA4681
I
2
C-BUS PROTOCOL
Control
The I
2
C-bus transmitter/receiver provides the data bytes to
select and adjust the following functions and parameters:
Brightness adjust
Saturation adjust
Contrast adjust
Hue control voltage
RGB gain adjust
RGB reference voltage levels
Peak drive limiting
Selection of the vertical blanking interval and
measurement lines for cut-off and white level control
according to transmission standard
Selects either 3-level or 2-level (5 V) sandcastle pulse
Enables/disables input clamping pulse delay
Enables/disables white level control
Enables cut-off control; enables output clamping
Enables/disables full screen white level
Enables/disables full screen black level
Selects either PAL/SECAM or NTSC matrix
Enables saturation adjust; enables nominal saturation
Enables/disables synchronization of the execution of
I
2
C-bus commands with the vertical blanking interval
Reads the result of the comparison of the nominal and
actual RGB signal levels for automatic white level
control.
I
2
C-bus transmitter/receiver and data transfer
I
2
C-
BUS SPECIFICATION
The I
2
C-bus is a bidirectional, two-wire, serial data bus for
intercommunication between ICs in a system.
The microcontroller transmits/receives data from the
I
2
C-bus transceiver in the TDA4681 over the serial data
line SDA (pin 27) synchronized by the serial clock line SCL
(pin 28). Both lines are normally connected to a positive
voltage supply through pull-up resistors. Data is
transferred when the SCL line is LOW. When SCL is HIGH
the serial data line SDA must be stable. A HIGH-to-LOW
transition of the SDA line when SCL is HIGH is defined as
a START bit. A LOW-to-HIGH transition of the SDA line
when SCL is HIGH is defined as a STOP bit.
Each transmission must start with a START bit and end
with a STOP bit. The bus is busy after a START bit and is
only free again after a STOP bit has been transmitted.
I
2
C-
BUS RECEIVER
(
MICROCONTROLLER WRITE MODE
)
Each transmission to/from the I
2
C-bus transceiver
consists of at least three bytes following the START bit.
Each byte is acknowledged by an acknowledge bit
immediately following each byte. The first byte is the
Module Address (MAD) byte, also called the slave address
byte. This consists of the module address, 1000100 for the
TDA4681, plus the R/W bit (see Fig.4). When the
TDA4681 is a slave receiver (R/W = 0) the module
address byte is 10001000 (88H). When the TDA4681 is a
slave transmitter (R/W = 1) the module address byte is
10001001 (89H).
The length of a data transmission is unrestricted, but the
module address and the correct subaddress must be
transmitted before the data byte(s). The order of data
transmission is shown in Figs 5 and 6.
Without auto-increment (BREN = 0 or 1) the module
address (MAD) byte is followed by a SubAddress (SAD)
byte and one data byte only (see Fig.5).
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