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參數(shù)資料
| 型號： | TDA4885 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | 150 MHz video controller with I2C-bus |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP32 |
| 封裝： | 0.400 INCH, PLASTIC, SOT-232-1, SDIP-32 |
| 文件頁數(shù)： | 31/56頁 |
| 文件大?。?/td> | 396K |
| 代理商： | TDA4885 |
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1997 Nov 25
31
Philips Semiconductors
Product specification
150 MHz video controller with I
2
C-bus
TDA4885
Table 3
Subaddress byte and data byte format
Notes
1.
2.
3.
The least significant bit (LSB) of an analog alignment register is defined as AX0 (data bit D0).
Data bit.
After power-on reset control and test register are reset to logic 0 and all alignment registers are set to logic 0
(minimum).
X means don’t care but for software compatibility with other video ICs with the same slave address, they are
preferably set to logic 0.
For production tests only.
4.
5.
Table 4
Control register
FUNCTION
SUB-
ADDRESS
DATA BYTE
(1)
NOMINAL
VALUE
(3)
D7
(2)
D6
(2)
D5
(2)
D4
(2)
X
(4)
X
(4)
X
(4)
X
(4)
X
(4)
X
(4)
X
(4)
X
(4)
X
(4)
X
(4)
X
(4)
X
(4)
X
(4)
X
(4)
A77
A76
A87
A86
A97
A96
D3
(2)
D2
(2)
D1
(2)
D0
(2)
Control register
Brightness control
Contrast control
OSD contrast control
Gain control channel 1
Gain control channel 2
Gain control channel 3
Black level reference channel 1
Black level reference channel 2
Black level reference channel 3
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
X
(4)
A15
A25
X
(4)
A45
A55
A65
A75
A85
A95
X
(4)
A14
A24
X
(4)
A44
A54
A64
A74
A84
A94
FPOL DISV DISO
A13
A12
A23
A22
A33
A32
A43
A42
A53
A52
A63
A62
A73
A72
A83
A82
A93
A92
PEDST
A10
A20
A30
A40
A50
A60
A70
A80
A90
A11
A21
A31
A41
A51
A61
A71
A81
A91
10H
26H
0FH
3FH
3FH
3FH
0AH to 0EH not used
0FH
Reserved (note 5)
X
(4)
X
(4)
X
(4)
X
(4)
X
(4)
0
0
0
BIT
FUNCTION
PEDST = 0
PEDST = 1
DISO = 0
DISO = 1
DISV = 0
DISV = 1
FPOL = 0
FPOL = 1
no pedestal blanking
pedestal blanking enabled
OSD signals enabled
OSD signals disabled
video signals enabled
video signals disabled
negative feedback polarity
positive feedback polarity
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