參數(shù)資料
型號: TDA5153AG
廠商: NXP SEMICONDUCTORS
元件分類: 光電元器件
英文描述: Pre-amplifier for Hard Disk Drive HDD with MR-read/inductive write heads
中文描述: 6 CHANNEL READ WRITE AMPLIFIER CIRCUIT, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-313, LQFP-48
文件頁數(shù): 15/28頁
文件大?。?/td> 128K
代理商: TDA5153AG
1997 Jul 02
15
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
Notes
1.
Not used bits in the registers (indicated by X) are don’t care. Default data, initialized at power-up, is zero in all
registers. For V
CC
< 2.5 V, the register contents are not guaranteed.
V
th
programming uses both test mode register and compensation capacitor register. d0 in the formula above is the
LSB of the test mode register and b2 is the data bit d2 of the compensation register.
2.
0
0
1
1
0
0
1
0
MR current DAC register:
0
1
0
0
0
0
1
0
write current DAC register:
ext
0
1
0
1
0
0
1
0
servo write register:
(d0, d1) = (0, 0) = one head
(d0, d1) = (1, 1) = all heads
test mode register:
(d2,d1,d0) = (0,0,0) = not in test mode
(d2,d1,d0) = (0,0,1) = read head test (I
MR1
= I
MR2
)
(d2,d1,d0) = (0,1,0) = read head test (I
MR2
= 5 mA fixed)
(d2,d1,d0) = (0,1,1) = temperature monitor
(d2,d1,d0) = (1, X, d0) = thermal asperity detection
0
1
1
0
0
0
1
0
, see note 2
0
1
1
1
0
0
1
0
compensation capacitor register:
equivalent differential capacitance:
high frequency gain attenuator register:
1
0
0
0
0
0
1
0
nominal pole frequency:
1
0
0
1
0
0
1
0
high-frequency gain boost register:
nominal zero frequency:
1
0
1
0
0
0
1
0
settle time register:
settle time:
1
1
1
1
0
0
1
1
chip ID register:
, d3 to d0 are preset to (0, 0, 1, 1)
a7
a6
a5
a4
0
0
1
1
when a0 = 1, data from the register with address a7 to a4 is read out on
SDATA
A7 A6 A5 A4 A3 A2 A1 A0
DESCRIPTION
I
MR
0.5
ext
R
×
10
16 d4
8 d3
4 d2
2 d1
1 d0
+
+
+
+
+
(
)
mA
×
=
I
WR
R
20
16 d4
8 d3
4 d2
2 d1
1 d0
+
+
+
+
+
(
)
mA
×
=
V
th
210
560 d0
280 b2
+
+
(
) μ
V
=
4 d2
2 d1
1 d0
+
+
(
)
2 pF
×
4 d2
8 d3
2 d1
1 d0
+
+
+
--------------------------800 MHz
2 d1
1 d0
+
+
+
8 d3
t
st
2
4 d2
2 d1
1 d0
1
+
+
+
(
)
----------------------------------1
μ
s
+
=
ID
8 d3
4 d2
2 d1
1 d0
+
+
+
=
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