- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368629 > TDA5153X (NXP SEMICONDUCTORS) Pre-amplifier for Hard Disk Drive HDD with MR-read/inductive write heads PDF資料下載
參數(shù)資料
| 型號： | TDA5153X |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 光電元器件 |
| 英文描述： | Pre-amplifier for Hard Disk Drive HDD with MR-read/inductive write heads |
| 中文描述： | 6 CHANNEL READ WRITE AMPLIFIER CIRCUIT, UUC48 |
| 封裝： | DIE |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 128K |
| 代理商： | TDA5153X |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
1997 Jul 02
11
Philips Semiconductors
Preliminary specification
Pre-amplifier for Hard Disk Drive (HDD)
with MR-read/inductive write heads
TDA5153
8.4
Standby mode
The circuit can be put in standby mode using the serial
interface. In standby mode, typical DC current
consumption is 330
μ
A. Transients from standby mode to
active mode are two orders of magnitude shorter than from
sleep mode to active mode. This is important in the case
of cylinder mode operation with multiple amplifiers.
All amplifiers can operate from standby mode and all head
switch times can be kept just as short as in the case of
operation with a single amplifier. Head switching times are
summarized in the switching characteristics.
8.5
Active mode
Active mode is either read mode or write mode depending
on the R/W pin.
8.6
Bi-directional serial interface
The serial interface is used for programming of the device
and for reading of status information. 16 bits (8 bits for
data and 8 for address) are used to program the device.
The serial interface requires 3 pins: SDATA, SCLK and
SEN. These pins (and R/W) are CMOS inputs. The logic
input R/W has an internal 20 k
pull-up resistor and the
SEN logic input has an internal 20 k
pull-down resistor.
Thus, in case the SEN line is opened, no data will be
registered and in case the R/W line is opened, the device
will never be in write mode.
SDATA: serial data; bi-directional data interface. In all
circumstances,
the LSB is transmitted first
.
SCLK: serial clock; 25 MHz clock frequency.
SEN: serial enable; data transfer takes place when SEN is
HIGH. When SEN is LOW, data and clock signals are
prohibited from entering the circuit.
Three phases in the communication are distinguishable:
addressing, programming and reading. Each
communication sequence starts with an addressing
phase, followed by either a programming phase or a
reading phase.
8.7
Addressing
When SEN goes HIGH, bits are latched in at rising edges
of SCLK. The first eight bits a7 to a0, starting with a0, are
shifted serially into an address register. If SEN goes LOW
before 16 bits have been received, the operation is
ignored. When more than 16 bits (address and data) are
latched in before SEN goes LOW, the first 8 bits are
interpreted as an address and the last 8 bits as data.
SEN should go HIGH at least 5 ns before the first rising
edge of SCLK. Data should be valid at least 5 ns before
and after a rising edge of SCLK. The bits a7 to a4
constitute the register address.To validate the
communication with the preamplifier, bits a1, a2 and a3
have to be programmed as (1, 0, 0).
If bit a0 = logic 0, a programming sequence starts.
If bit a0 = logic 1, reading data from the pre-amplifier can
start.
8.8
Programming data
If a0 = logic 0, the last eight bits d7 to d0 before SEN goes
LOW are shifted into an input register. Bits d6 and d7 are
don’t care. When SEN goes LOW, the communication
sequence is ended and the data in the input register is
copied in parallel to the data register that corresponds to
the decoded address a7 to a4. SEN should go LOW at
least 5 ns after the last rising edge of SCLK.
8.9
Reading data
Immediately after the IC detects that a0 = logic 1, data
from the data register (address a7 to a4) is copied in
parallel to the input register. Two wait clock cycles must
follow before the controller can start inputting data. At the
first falling edge of SCLK after the 2 wait rising edges of
SCLK, the LSB d0 is placed on SDATA line followed by d1
at the next falling edge of SCLK etc. If SEN goes LOW
before 8 address bits (a7 to a0) have been detected, the
communication is ignored.
相關PDF資料 |
PDF描述 |
|---|---|
| TDA5153BG | Pre-amplifier for Hard Disk Drive HDD with MR-read/inductive write heads |
| TDA5634T | 9 V UHF mixer/oscillator for TV and VCR tuners |
| TDA5731M | Low power VHF, UHF andhyperband mixer/oscillator for TVand VCR 3-band tuners(應用于TV和 VCR三頻帶調諧的低功耗VHF，UHF和超頻帶混頻器/振蕩器) |
| TDA5732 | Low power VHF, UHF mixer/oscillator for TV and VCR 2-band tuners |
| TDA5732M | Low power VHF, UHF mixer/oscillator for TV and VCR 2-band tuners |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TDA5155 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Pre-amplifier for Hard Disk Drive HDD with MR-read/inductive write heads |
| TDA5155X | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Pre-amplifier for Hard Disk Drive HDD with MR-read/inductive write heads |
| TDA5200 | 功能描述:射頻接收器 CNTRL RF RECEIVER 870MHZ 5V RoHS:否 制造商:Skyworks Solutions, Inc. 類型:GPS Receiver 封裝 / 箱體:QFN-24 工作頻率:4.092 MHz 工作電源電壓:3.3 V 封裝:Reel |
| TDA5200_10 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:ASK Single Conversion Receiver |
| TDA5200T | 制造商:Infineon Technologies AG 功能描述:RF Receiver ASK 5V 28-Pin TSSOP T/R |
發(fā)布緊急采購，3分鐘左右您將得到回復。