參數(shù)資料
型號(hào): TDA5231
廠(chǎng)商: INFINEON TECHNOLOGIES AG
元件分類(lèi): 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PDSO28
封裝: GREEN, PLASTIC, TSSOP-28
文件頁(yè)數(shù): 33/186頁(yè)
文件大小: 3820K
代理商: TDA5231
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TDA523x
Functional Description
Data Sheet
124
Version 4.0, 2007-06-01
Read Register
Figure 66
Read Register
To read from the device, the chip must be selected first. Therefore, the master must set
the NCS line to low. After this, the instruction byte and the address byte are shifted in on
SDI and stored in the internal instruction and address register. The data byte at this
address is then shifted out on SDO. After completing the read operation the master sets
the NCS line to high.
Write Register
Figure 67
Write Register
To write to the device, the chip must be selected first. Therefore the master must set the
NCS line to low. After this, the instruction byte and the address byte are shifted in on SDI
and stored in the internal instruction and address register. The following data byte is then
stored at this address.
After completing the write operation, the master sets the NCS line to high.
Use of the SPI Trace Registers:
The received address byte is stored into the register SPIAT and the received data byte
is stored into the register SPIDT. These two trace registers are readable. Therefore, an
external controller is able to check the correct address and data transmission by reading
out these two registers after each write instruction. The trace registers are updated at
every write instruction, so only the last transmission can be checked by a read out of
these two registers.
Data Out
SDI
SDO
high impedance Z
SCK
NCS
D7 D6 D5 D4
Instruction
I7
I6
I3
I2
Register Address
I1
I0
Frame
I5
I4
A7 A6
A3 A2 A1 A0
A5 A4
D3 D2 D1
D7 D6 D5 D4
Instruction
Register Address
D3 D2 D1 D0
Data Out
Frame
18
D0
I7
I6
I3
I2
I1
I0
I5
I4
A7 A6
A3 A2 A1 A0
A5 A4
SDI
SDO
high impedance Z
SCK
NCS
Instruction
Frame
18
I7
I6
I3
I2
I1
I0
I5
I4
D7 D6 D5 D4
D1 D0
D3 D2
Register Address
18
Data Byte
18
Instruction
Frame
18
Register Address
18
Data Byte
18
A7 A6
A3 A2 A1 A0
A5 A4
I7
I6
I3
I2
I1
I0
I5
I4
D7 D6 D5 D4
D1 D0
D3 D2
A7 A6
A3 A2 A1 A0
A5 A4
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