參數(shù)資料
型號(hào)： TDA5251F1
廠商： INFINEON TECHNOLOGIES AG
英文描述： ASK/FSK 315MHz Wireless Transceiver
中文描述： 詢(xún)價(jià)/ FSK信號(hào)315MHz的無(wú)線收發(fā)器
文件頁(yè)數(shù)： 35/88頁(yè)
文件大?。?/td> 2086K
代理商： TDA5251F1
TDA5251 F1
Version 1.0
Functional Description
Preliminary Specification
35
2003-02-18
Confidential
Note:
Data are valid 500 μs after the crystal oscillator is enabled (see
Figure 2-15
and
Figure 2-
16
, tCLKSU).
Note:
As long as default settings are used, there is no clock available at the clock output during
Power Down. It is possible to enable the clock during Power Down by setting CLK_EN (Bit D9) in
the Config Register (00H) to HIGH.
2.4.20
RSSI and Supply Voltage Measurement
The input of the 6Bit-ADC can be switched between two different sources: the RSSI voltage (default
setting) or a resistor network dividing the Vcc voltage by 5.
Table 2-29
CLK_DIV Output Selection
D4
0
1
0
1
D5
0
0
1
1
Output
Output from Divider (default)
13.125MHz
32kHz
Window Count Complete
Table 2-30
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CLK_DIV Setting
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Total Divider Ratio
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
Output Frequency [MHz]
6.6
3.3
2.2
1.6
1.3
1.1
0.94
0.82
0.730 (default)
0.66
0.6
0.,55
0.5
0.47
0.44
0.41
Table 2-31
SELECT
Source for 6Bit-ADC Selection (Register 08H)
Input for 6Bit-ADC
0
1
Vcc / 5
RSSI (default)
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