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參數(shù)資料
| 型號(hào)： | TDA6612-2X |
| 廠商： | SIEMENS A G |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 文件頁數(shù)： | 34/47頁 |
| 文件大小： | 1967K |
| 代理商： | TDA6612-2X |
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Semiconductor Group
4
TDA 6612-2
center frequency of the filter is switched between "dual" and "stereo" by a multiplexer. The
multiplexing frequency is adjustable by software. If a side band is detected, the multiplexer stops.
The interferences on the first "detected" criterion are suppressed by a digital integrator with a
following comparator and can be read out via I2C Bus (talk mode) as the "stereo" or "dual" mode.
The control of the corresponding signal can be either directly internally or through the
C. All the
necessary clock signal are derived from a fast setting PLL which is synchronized by a reference
frequency. This reference frequency must be sufficiently close to the horizontal frequency, but a
rigid phase coupling is not required. Therefore, alternatively the use of a crystal controlled 62.5-
kHz frequency commonly found in PLL-tuning systems is possible. A further alternative for the clock
signal generation is a build-in crystal oscillator with an external 4-MHz crystal or the use an external
1- or 4-MHz clock frequency.
Control Section
All functions are controlled via an I2C Bus interface with "listen" / "talk" functions. The data bytes
currently used are stored in a block of latches.
The telegram structure is formed in the following manner:
start condition - chip address - any number of bytes - stop condition
The following conditions apply to the data bytes:
Before the actual data byte (with the adjustment information), always an I2C Bus sub-address byte
has to be transmitted. The I2C Bus interface however is interpreting this sub-address byte as a data
byte.
Example: The headphone volume is to be increased in a number of steps.
Within a telegram (i.e. without a new start condition) any different sub-addresses can be accessed.
The changeover between "listen" and "talk" access to the IC however must always occur using the
following sequence: stop condition - start condition - chip address. Before each read access always
a start condition and chip address (talk) must be transmitted. The data to be read out are then
loaded into the I2C Bus interface and can be transferred to the
C.
Right
Wrong
Start condition
Chip address 84 (Hex)
Sub-addr. vol. HP 03 (Hex)
Vol. step 8 08 (Hex)
Sub-addr. vol. HP 03 (Hex)
Vol. step 9 09 (Hex)
Sub-addr. vol. HP 03 (Hex)
Vol. step 10 0A (Hex)
Stop condition
Start condition
Chip address 84 (Hex)
Sub-addr. vol. HP 03 (Hex)
Vol. step 8 08 (Hex)
Vol. step 9 09 (Hex)
Vol. step 10 0A (Hex)
Stop condition
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