參數(shù)資料
型號： TDA6650ATT/C3/S2
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PDSO38
封裝： 4.40 MM, 0.50 MM PITCH, PLASTIC, MO-153, SOT510-1, TSSOP-38
文件頁數(shù)： 2/54頁
文件大?。?/td> 325K
代理商： TDA6650ATT/C3/S2
TDA6650ATT_6651ATT_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 2 February 2007
10 of 54
NXP Semiconductors
TDA6650ATT; TDA6651ATT
5 V mixer/oscillator and low noise PLL synthesizer
8.1.1 I2C-bus address selection
The device address contains programmable address bits MA1 and MA0, which offer the
possibility of having up to four MOPLL ICs in one system. Table 8 gives the relationship
between the voltage applied to the AS input and the MA1 and MA0 bits.
8.1.2 XTOUT output buffer and mode setting
The crystal frequency can be sent to pin XTOUT and used in the application, for example
to drive the clock input of a digital demodulator, saving a quartz crystal in the bill of
material. To output fxtal, it is necessary to set T[2:0] to 001. If the output signal on this pin
is not used, it is recommended to disable it, by setting T[2:0] to 000. This pin is also used
to output 1
2fdiv and fcomp in a test mode. At power-on, the XTOUT output buffer is set to
on, supplying the fxtal signal. The relation between the signal on pin XTOUT and the
setting of the T[2:0] bits is given in Table 9.
[1]
This is an on-chip function that automatically sets internal values for the PLL. This function is not optimized
for ISDB-T and NTSC Japan and therefore must not be used.
[2]
This is the default mode at power-on reset. This mode disables the tuning voltage.
8.1.3 Step frequency setting
The step frequency is set by three bits, giving ve steps to cope with different application
requirements.
The reference divider ratio is automatically set depending on bits R2, R1 and R0. The
phase detector works at either 4 MHz, 2 MHz or 1 MHz.
Table 10 shows the step frequencies and corresponding reference divider ratios. When
the value of bits R2, R1 and R0 are changed, it is necessary to re-send the data bytes
DB1 and DB2.
Table 8.
Address selection
Voltage applied to pin AS
MA1
MA0
0 V to 0.1VCC
00
0.2VCC to 0.3VCC or open-circuit
0
1
0.4VCC to 0.6VCC
10
0.9VCC to VCC
11
Table 9.
XTOUT buffer status and test modes
T2
T1
T0
Pin XTOUT
Mode
0
disabled
normal mode with XTOUT buffer off
001fxtal (4 MHz)
normal mode with XTOUT buffer on
010
1
2fdiv
charge pump off
011fxtal (4 MHz)
not used[1]
100fcomp
test mode
101
1
2fdiv
test mode
110fxtal (4 MHz)
charge pump sinking current[2]
1
disabled
charge pump sourcing current
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