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| 型號： | TDA6650TT |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog) |
| 中文描述： | 5伏混頻器/振蕩器，低噪聲的混合型地面調(diào)諧器鎖相環(huán)頻率合成器（數(shù)字和模擬） |
| 文件頁數(shù)： | 8/55頁 |
| 文件大?。?/td> | 377K |
| 代理商： | TDA6650TT |
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2004 Mar 22
8
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
It is possible to drive the clock input of a digital
demodulation IC from pin XTOUT with the 4 MHz signal
from the crystal oscillator. This output is also used to
output
1
/
2
f
div
and f
comp
signals in a specific test mode (see
Table 6). It is possible to switch off this output, which is
recommended when it is not used.
For test and alignment purposes, it is also possible to
release the tuning voltage output by selecting the sinking
mode (see Table 6), and by applying an external voltage
on pin VT.
In addition to the BS1 and BS2 output ports that are used
for the band selection, there are three general purpose
ports BS3, BS4 and BS5. All five ports are PMOS
open-drain type, each with 15 mA drive capability. The
connection for port BS5 and the ADC input is combined on
one pin. It is not possible to use the ADC if port BS5 is
used.
The AGC detector compares the level at the IF amplifier
output to a reference level which is selected from
6 different levels via the I
2
C-bus. The time constant of the
AGC can be selected via the I
2
C-bus to cope with normal
operation as well as with search operation.
When the output level on pin AGC is higher than the
threshold V
RMH
, then bit AGC = 1. When the output level
on pin AGC is lower than the threshold V
RML
, then
bit AGC = 0. Between these two thresholds, bit AGC is not
defined. The status of the AGC bit can be read via the
I
2
C-bus according to the read mode as described in
Table 12.
7.2
I
2
C-bus voltage
The I
2
C-bus lines SCL and SDA can be connected to an
I
2
C-bus system tied to 2.5, 3.3 or 5 V. The choice of the
businput thresholdvoltages ismadewith pin BVSthat can
be left open-circuit, connected to the supply voltage or to
ground (see Table 2).
Table 2
I
2
C-bus voltage selection
7.3
Phase noise, I
2
C-bus traffic and crosstalk
WhiletheTDA6650TT;TDA6651TTisdedicatedforhybrid
terrestrial applications, the low noise PLL will clean up the
noise spectrum of the VCOs close to the carrier to reach
noiselevelsat1 kHzoffsetfromthecarriercompatiblewith
e.g. DVB-T reception.
Linked to this noise improvement, some disturbances may
become visible while they were not visible because they
were hidden into the noise in analog dedicated
applications and circuits.
This is especially true for disturbances coming from the
I
2
MOPLL or for another slave on the bus.
To avoid this I
2
C-bus crosstalk and be able to have a clean
noise spectrum, it is necessary to use a bus gate that
enables the signal on the bus to drive the MOPLL only
when the communication is intended for the tuner part
(such a kind of I
2
C-bus gate is included into the Philips
terrestrial channel decoders), and to avoid unnecessary
repeated sending of the same information.
8
I
2
C-BUS PROTOCOL
The TDA6650TT; TDA6651TT is controlled via the
two-wire I
2
C-bus. For programming, there is one device
address (7 bits) and the R/W bit for selecting read or write
mode. To be able to have more than one MOPLL in an
I
2
C-bussystem,oneoffourpossibleaddressesisselected
depending on the voltage applied to address selection
pin AS (see Table 5).
The TDA6650TT; TDA6651TT fulfils the fast mode
I
2
C-bus,accordingtothePhilipsI
2
C-busspecification(see
Chapter 20), except for the timing as described in Fig.4.
The I
2
C-bus interface is designed in such a way that the
pins SCL and SDA can be connected to 5, 3.3 or to 2.5 V
pulled-up I
2
C-bus lines, depending on the voltage applied
to pin BVS (see Table 2).
PIN BVS
CONNECTION
BUS
VOLTAGE
LOGIC LEVEL
LOW
HIGH
To ground
Open-circuit
To V
CC
2.5 V
3.3 V
5 V
0 to 0.75 V
0 to 1.0 V
0 to 1.5 V
1.75 to 5.5 V
2.3 to 5.5 V
3.0 to 5.5 V
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA6650TT/C3 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog) |
| TDA6650TT/C3/S2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog) |
| TDA6651 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog) |
| TDA6651ATT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog) |
| TDA6651ATT/C3 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog) |
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