參數(shù)資料
型號(hào): TDA6651
廠商: NXP Semiconductors N.V.
英文描述: 5 V mixer/oscillator and low noise PLL synthesizer for hybrid terrestrial tuner (digital and analog)
中文描述: 5伏混頻器/振蕩器,低噪聲的混合型地面調(diào)諧器鎖相環(huán)頻率合成器(數(shù)字和模擬)
文件頁(yè)數(shù): 14/55頁(yè)
文件大?。?/td> 377K
代理商: TDA6651
2004 Mar 22
14
Philips Semiconductors
Product specification
5 V mixer/oscillator and low noise PLL synthesizer
for hybrid terrestrial tuner (digital and analog)
TDA6650TT;
TDA6651TT
8.2
Read mode; R/W = 1
Data can be read from the device by setting the R/W bit
to 1 (see Table 12). After the device address has been
recognized, the device generates an acknowledge pulse
and the first data byte (status byte) is transferred on the
SDA line (MSB first). Data is valid on the SDA line during
a HIGH level of the SCL clock signal.
A second data byte can be read from the device if the
microcontroller generates an acknowledge on the SDA
line (master acknowledge). End of transmission will occur
if no master acknowledge occurs. The device will then
release the data line to allow the microcontroller to
generate a STOP condition.
Table 12
I
2
C-bus read data format
Note
1.
MSB is transmitted first.
Table 13
Description of read data format bits
NAME
BYTE
BIT
ACK
MSB
(1)
LSB
Address byte
Status byte
1
2
1
1
0
0
1
0
MA1
A2
MA0
A1
R/W = 1
A0
A
POR
FL
ALBC
AGC
BIT
DESCRIPTION
A
POR
acknowledge bit
Power-on reset flag
POR = 0, normal operation
POR = 1, Power-on reset
in-lock flag
FL = 0, not locked
FL = 1, the PLL is locked
automatic loop bandwidth control flag
ALBC = 0, no automatic loop bandwidth control
ALBC = 1, automatic loop bandwidth control selected
internal AGC flag
AGC = 0 when internal AGC is active (V
AGC
< V
RML
)
AGC = 1 when internal AGC is not active (V
AGC
> V
RMH
)
digital outputs of the 5-level ADC; see Table 14
FL
ALBC
AGC
A2, A1, A0
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