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參數(shù)資料
| 型號(hào)： | TDA7300 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | DIGITAL CONTROLLED STEREO AUDIO PROCESSOR |
| 中文描述： | 數(shù)控立體聲音頻處理器 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 288K |
| 代理商： | TDA7300 |
APPLICATION INFORMATION
(continued)
SERIALBUS INTERFACE
S-BUS Interfaceand I
2
CBUSCompatibility
Data transmission from microprocessor to the
TDA7300 and viceversa takes place thru the 3-
wire S-BUS interface, consisting of the three lines
SDA, SCL, SEN. If SDA and SEN inputs are
short-circuited together, then the TDA7300 ap-
pears as a standardI
2
CBUS slave.
According to I
2
CBUS specification the S-BUS
lines are connected to a positive supply voltage
via pull-up resistors.
DataValidity
As shown in fig. 21, the data on the SDA line
mustbe stableduring the high period of the clock.
The HIGH and LOW state of the data line can
only change when the clock signal on the SCL
line is LOW.
Figure21:
Data Validity on the I
2
CBUS
Startand Stop Conditions
I
2
CBUS:
as shown in fig.22 a start condition is a HIGH to
Figure22:
Timing Diagram of S-BUSand I
2
CBUS
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
S-bus:
the start/stop conditions (points 1 and 6) are de-
tected exclusively by a transition of the SEN line
(1
→
0 / 0
→
1) while the SCLline is at the HIGH
level.
The SDA line is only allowed to change duringthe
time the SCL line is low (points 2, 3, 4, 5). After
the start information(point 1) the SEN line returns
to the HIGH level and remains unchanged for all
the time the transmission is performed.
Byte Format
Every byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledgebit. The MSB is transferredfirst.
Acknowledge
The master (
μ
P) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 23). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDAline is stableLOWduringthis clockpulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
TDA7300
10/16
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相關(guān)代理商/技術(shù)參數(shù) |
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| TDA7300D | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DIGITAL CONTROLLED STEREO AUDIO PROCESSOR |
| TDA7303 | 功能描述:音頻放大器 Digital CNTRL Stereo Audio Processor LOU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| TDA7303TR | 功能描述:音頻放大器 Digital CNTRL Stereo Audio Processor LOU RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| TDA7309 | 功能描述:音頻 DSP Digital Audio Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TDA7309_06 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:DIGITAL CONTROLLED STEREO AUDIO PROCESSOR WITH LOUDNESS |
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