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參數(shù)資料
| 型號： | TDA7318 |
| 廠商： | 意法半導體 |
| 英文描述： | Digital Controlled Stereo Audio Processor(數(shù)控立體聲音頻處理器) |
| 中文描述： | 數(shù)控立體聲音頻處理器（數(shù)控立體聲音頻處理器） |
| 文件頁數(shù)： | 8/14頁 |
| 文件大?。?/td> | 248K |
| 代理商： | TDA7318 |
I
2
C BUS INTERFACE
Data transmission from microprocessor to the
TDA7318 and viceversa takes place thru the 2
wires I
2
C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
DataValidity
As shown in fig. 14, the data on the SDA line
mustbe stableduring the high period of the clock.
The HIGH and LOW state of the data line can
only change when the clock signal on the SCL
line is LOW.
Startand Stop Conditions
As shown in fig.15 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop conditionis a LOW to HIGH tran-
sitionof the SDAline while SCLis HIGH.
Byte Format
Every byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
knowledgebit. The MSB is transferredfirst.
Acknowledge
The master (
μ
P) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 16). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during the acknowledge clock pulse, so that the
SDAline is stableLOWduringthis clockpulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
TransmissionwithoutAcknowledge
Avoiding to detect the acknowledge of the audio-
processor, the
μ
P can use a simplier transmis-
sion: simply it waits one clock without checking
the slave acknowledging, and sends the new
data.
This approach of course is less protected from
misworking and decreasesthe noise immunity.
Figure14:
Data Validity on the I
2
CBUS
Figure15:
Timing Diagram of I
2
CBUS
Figure16:
Acknowledgeon the I
2
CBUS
TDA7318
8/14
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TDA7318D | 功能描述:IC PROCESSOR STEREO DGTL 28-SOIC RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:- 其它有關(guān)文件:STA321 View All Specifications 標準包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
| TDA7318D013TR | 功能描述:音頻 DSP Digital Audio Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TDA7319 | 功能描述:音頻 DSP Digital Audio Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| TDA7319D | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3 BAND DIGITAL CONTROLLED AUDIO PROCESSOR |
| TDA7326 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:AM-FM RADIO FREQUENCY SYNTHESIZER |
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