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參數(shù)資料
| 型號(hào)： | TDA7326D |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | AM-FM RADIO FREQUENCY SYNTHESIZER |
| 中文描述： | 上午調(diào)頻射頻合成器 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大小： | 184K |
| 代理商： | TDA7326D |
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ELECTRICAL CHARACTERISTICS
(continued)
LOOP FILTER OUTPUT
(LP
OUT
= PIN 14)
Symbol
v
OL
V
OH
CHARGE PUMP CURRENT GENERATION
(LP
IN1
, LP
IN2
= PIN 15, 16)
Parameter
Test Condition
ILOAD = 0.2mA V
DD2
; = 10V
-ILOAD = 0.2mA V
DD2
; = 10V
Min.
Typ.
0.5
9.5
Max.
0.8
Unit
V
V
Output Voltage Low
Output Voltage High
9
I
si
Sink Current LPIN1,2
CURR1 = 0, CURR2 = 0
CURR1 = 0, CURR2 = 1
CURR1 = 1, CURR2 = 1
CURR1 = 1, CURR2 = 0
CURR1 = 0, CURR2 = 0
CURR1 = 0, CURR2 = 1
CURR1 = 1, CURR2 = 1
CURR1 = 1, CURR2 = 0
2
5
7
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
120
180
370
2
120
180
370
200
300
500
5
200
300
500
280
420
630
7
280
420
630
-I
so
Source Current LPIN1,2
DOUT1 OPENDRAIN OUTPUT
(PIN 9)
v
OL
Output Voltage Low
ILOAD = 1mA
0.2
0.5
V
BUS INTERFACE
-I
IL
I
IH
v
IH
V
IL
Input Leakage Current
Input Leakage Current
Input Voltage High
Input Voltage Low
VIN = V
SS
VIN = V
SS
Leading edge
Leading edge
-1
-1
3.4
0.1
0.1
4.0
1.0
1
1
μ
A
μ
A
V
V
1.6
BUS INTERFACE, WAITINGTIME
(see fig. 5) The Data is Acquired at the High
→
Low Clock Transition
t
1
t
3
t
5
CLK Low to DLEN L
→
H
DATA Transition to CLK H
→
L
CLK H
→
L to DATA Transition
BUS INTERFACE, DATA REPETITION TIME
(see fig. 5)
0.2
0.1
0.4
μ
s
μ
s
μ
s
t
r1
Release Time Between 2 bytes,
except byte 4
Release Time after the
transmission of byte 4
5
μ
s
t
r2
FM mode
AM mode
180
2
μ
s
ms
BUS INTERFACE, SETUPTIME
(see fig.5)
t
2
DLEN High to CLK L
→
H
0.1
μ
s
BUS INTERFACE, HOLD TIME
(see fig. 5)
t
4
t
6
DATA Transition to CKL L
→
H
CLK H
→
L to DLEN H
→
L
CLK Frequency
Duty Cycle
Clock Pulse Low
Clock Pulse High
0
μ
s
μ
s
KHz
%
μ
s
μ
s
0.4
f
CLK
500
50
t
pl
t
ph
1
1
TDA7326
4/16
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