參數(shù)資料
型號(hào): TDA7421
廠商: 意法半導(dǎo)體
英文描述: AM/FM TUNER FOR CAR RADIO AND Hi-Fi APPLICATIONS
中文描述: AM / FM調(diào)諧的汽車收音機(jī)及音響應(yīng)用
文件頁數(shù): 16/38頁
文件大?。?/td> 527K
代理商: TDA7421
quency. In FM mode a 6.25 KHz, in AM mode a
1KHz signal is generated. This counter is fol-
lowed by an asynchronous divider to generate
several sampling times.
Intermediate Frequency Main Counter (IFMC)
This counter is a 13-21 bit synchronous autore-
load down-counter. Four bits are programmable
to have the possibility for an adjust to the fre-
quency of the IF filter.
The counter length is automatically adjusted to
the chosen sampling time and the counter mode.
At the start the counter will be loaded with a de-
fined value which is an equivalent to the divider
value (t
sample
f
IF
).
If a correct frequency is applied to the IF counter
frequency inputs IF-AM and IF-FM, at the end of
the sampling time the main counter is changing
its state from 0 to 1FFFFFH.
This is detected by a control logic. The frequency
range inside which a successful count results is
detected is adjustable setting bits EW 0, 1, 2.
Up-down counter filter
The information coming from the IF main counter
control logic is shifted into a 5 bit up down
counter circuit clocked by the sampling time sig-
nal. At the start (rising edge of the IFENA signal)
the counter is set to 10H and the SSTOP signal is
forced to "1".
Only when the counter reaches the value 10H -
step, SSTOP goes to "0".
SSTOP will be "1" again, if the counter reaches
the value 10h + step.
MSB
BIT 7
LPIN1/2
PC7
PC15
RC7
LSB
FUNCTION
PLL CHARGE PUMP
PLL COUNTER
PLL COUNTER
PLL REF
COUNTER
PLL REF
COUNTER
PLL LOCK
DETECT
IFC REF COUNTER
IFC REF COUNTER
IFC CONTROL
IFC CONTROL
SUBAD
00H
01H
02H
03H
BIT 6
CURRH
PC6
PC14
RC6
BIT 5
B1
PC5
PC13
RC5
BIT 4
B0
PC4
PC12
RC4
BIT 3
A3
PC3
PC11
RC3
BIT 2
A2
PC2
PC10
RC2
BIT 1
A1
PC1
PC9
RC1
BIT 0
A0
PC0
PC8
RC0
04H
RC15
RC14
RC13
RC12
RC11
RC10
RC9
RC8
05H
LDENA
-
D3
D2
D1
D0
PM1
PM0
06H
07H
08H
09H
IRC7
IFCM1
IFENA
IFS2
IRC6
IFCM0
-
IFS1
IRC5
IRC13
-
IFS0
IRC4
IRC12
-
CF4
IRC3
IRC11
-
CF3
IRC2
IRC10
EW2
CF2
IRC1
IRC9
EW1
CF1
IRC0
IRC8
EW0
CF0
ADDRESS ORGANIZATION
(PLL and IF Counter)
REF OSC IN
REGISTER
R0 ...R15
DIVIDER
: R
I
2
C bus
PD
AM IN
FM IN
REGISTER
PC0 ...PC4
COUNTER
A
PRESCALER
32/33
REGISTER
PC5 ... P15
DIVIDER
: B
fref
fsyn
D96AU545
fosc
I
2
C bus
I
2
C bus
(O/I)
FM and AM operation (swallow mode)
CURR HIGH
LOCKENA
LOCK
CHARGE PUMP
CURRENT
D96AU548
Charge Pump Logic
TDA7421
16/38
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