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參數(shù)資料
| 型號(hào)： | TDA7427AD |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 200 MHz, PDSO28 |
| 封裝： | TSSOP-28 |
| 文件頁(yè)數(shù)： | 21/22頁(yè) |
| 文件大?。?/td> | 444K |
| 代理商： | TDA7427AD |
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DIVIDER FROM VCO FREQUENCY TO
REFERENCE FREQUENCY
This divider provides a low frequency fSYN which
phase is compared with the reference frequency
fREF. It is controlled by the registers PC0 to PC4
and PC5 to PC15
OPERATING MODES
Four operating modes are available fo PLL; they
are user programmable with the Mode PM regis-
ters (see table below).
PM0
PM1
Operating Mode
0
Standby
1
0
AM (swallow)
0
1
AM (direct)
11
FM
- Standby mode: in this mode all device func-
tions are stopped. This allows low current
consumption without loss of information in all
registers. The pin LP-OUT is forced to 0V,
and all data registers are set to EFH. The os-
cillator keeps running.
- FM and AM (SW) Swallow Mode (SW):
in this mode the FM or AM signal is applied to
a 32/33 prescaler, which is controlled by a 5
bit divider ’A’.The 5 bit register (PC0 to PC4)
controls this divider. In parallel the output of
the prescaler is connected to a 11 bit divider
’B’. (PC5 to PC15).
fOSC = (R+1)
fREF
Dividing range calculation :
fVCO = [ 33
A + (B + 1 - A) 32 ] fREF
fVCO = (32
B + A + 32) fREF
Important: for correct operation A
≤ 32, B ≥ A, with
A and B variable values of the dividers).
- AM direct mode: the AM signal is applied di-
rectly to the 16 bit static divider ’C’. (PC0 to
PC15)
fOSC = (R + 1)
f REF
Dividing range:
fVCO = (C + 1)
fREF
THREE STATE PHASE COMPARATOR
The phase comparator generates a phase error
signal according to phase difference between
fSYN and fREF. This phase error signal drives the
charge pump current generator (fig. 3)
CHARGE PUMP CURRENT GENERATOR
This stage generates signed pulses of current.
The phase error signal decides the duration and
polarity of those pulses.
The current absolute values are programmable by
A0, A1, A2 registers for high current and B0, B1,
registers for low current.
LOW NOISE CMOS OP-AMP
An internal voltage divider at pin VREF connects
the positive input of the low noise Op-Amp. The
charge pump output connects the negative input.
This internal amplifier in cooperation with external
components can provide an active filter.
OSC IN
REGISTER
RC0 ... RC15
PREDIVIDER
: R
PHASE
DETECTOR
AM IN
FM IN
REGISTER
PC0 ... PC15
PRESCALER
: C
fref
fsyn
D95AU376A
TO CHARGE
PUMP
Figure 2. AM direct mode operation for SW, MW and LW
TDA7427A
8/21
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