參數(shù)資料
型號: TDA7430
廠商: STMICROELECTRONICS
元件分類: 音頻控制
英文描述: 2 CHANNEL(S), TONE CONTROL CIRCUIT, PQFP44
封裝: 10 X 10 MM, 1.40 MM HEIGTH, TQFP-44
文件頁數(shù): 23/23頁
文件大小: 229K
代理商: TDA7430
9/23
TDA7430 - TDA7431
3I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7430/TDA7431 and viceversa takes place through the 2
wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage
must be connected).
3.1 Data Validity
As shown in fig. 8, the data on the SDA line must be stable during the high period of the clock. The HIGH and
LOW state of the data line can only change when the clock signal on the SCL line is LOW.
3.2 Start and Stop Conditions
As shown in fig.9 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
3.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transferred first.
3.4 Acknowledge
The master (
P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 10).
The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during this clock
pulse.
The audioprocessor which has been addressed has to generate an acknowledge after the reception of each
byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master
transmitter can generate the STOP information in order to abort the transfer.
3.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audioprocessor, the
P can use a simpler transmission: simply it
waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
d
Distorsion
Av = 0 ; Vin = 1Vrms
0.01
0.1
%
SC
Channel Separation
70
90
dB
VOCL
Clipping Level
d = 0.3%
2
2.5
Vrms
ROUT
Output Resistance
10
40
70
VOUT
DC Voltage Level
3.8
V
BUS INPUTS
VIL
Input Low Voltage
1V
VIH
Input High Voltage
3
V
IIN
Input Current
-5
+5
mA
VO
Output Voltage SDA
Acknowledge
IO = 1.6mA
0.4
V
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Table 5. Electrical Characteristcs (continued)
相關(guān)PDF資料
PDF描述
TDA7430TR 2 CHANNEL(S), TONE CONTROL CIRCUIT, PQFP44
TDA7431S 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDIP42
TDA7431 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDIP42
TDA7438 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDIP28
TDA7438D 2 CHANNEL(S), TONE CONTROL CIRCUIT, PDSO28
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