參數(shù)資料
型號: TDA7564
廠商: 意法半導體
英文描述: MULTIFUNCTION QUAD POWER AMPLIFIER WITH BUILT-IN DIAGNOSTICS FEATURES
中文描述: 多功能四功率放大器,內(nèi)置診斷特征
文件頁數(shù): 14/20頁
文件大?。?/td> 248K
代理商: TDA7564
TDA7564
14/20
I
2
C BUS INTERFACE
Data transmission from microprocessor to the TDA7564 and viceversa takes place through the 2 wires I
2
C BUS inter-
face, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected).
Data Validity
As shown by fig. 22, the data on the SDA line must be stable during the high period of the clock. The HIGH and
LOW state of the data line can only change when the clock signal on the SCL line is LOW.
Start and Stop Conditions
As shown by fig. 23 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transferred first.
Acknowledge
The transmitter* puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 24).
The receiver** the acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so
that the SDAline is stable LOW during this clock pulse.
* Transmitter
= master (
μ
P) when it writes an address to the TDA7564
= slave (TDA7564) when the
μ
P reads a data byte from TDA7564
** Receiver
= slave (TDA7564) when the
μ
P writes an address to the TDA7564
= master (
μ
P) when it reads a data byte from TDA7564
Figure 22. Data Validity on the I
2
CBUS
Figure 23. Timing Diagram on the I
2
CBUS
Figure 24. Acknowledge on the I
2
CBUS
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
SCL
SDA
START
I
2
CBUS
STOP
D99AU1032
SCL
1
MSB
2
3
7
8
9
SDA
START
ACKNOWLEDGMENT
FROM RECEIVER
D99AU1033
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