參數(shù)資料
型號： TDA8043H
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： Satellite Demodulator and Decoder SDD
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： 14 X 20 X 2.80 MM, PLASTIC, QFP-100
文件頁數(shù)： 4/16頁
文件大小： 95K
代理商： TDA8043H
1998 Feb 13
4
Philips Semiconductors
Product specification
Satellite Demodulator and Decoder (SDD)
TDA8043
QUICK REFERENCE DATA
Notes
1.
These values are specified for a symbol rate of 27.5 Msymbols/s, a puncturing rate of
3
4
and a clock frequency of
65 MHz.
A range from 3 to 32 Msymbols/s can be achieved with one SAW filter. By using an internal clock divider and
reducing the external SAW filter bandwidth, symbol rates down to 0.5 Msymbols/s can be achieved by using a
65 MHz crystal clock.
This data was measured in a laboratory environment at a symbol rate of 27.5 Msymbols/s, a clock frequency of
65 MHz, a signal-to-noise ratio of 4.5 dB and including a tuner.
2.
3.
PINNING
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DDA
V
DDD
I
DD(tot)
f
clk
r
s
α
IL
S/N
analog supply voltage
digital supply voltage
total supply current
clock frequency
symbol rate
nyquist roll-off (selectable)
implementation loss
signal-to-noise ratio for locking
the SDD
total power dissipation
IC storage temperature
operating ambient temperature
operating junction temperature
3.0
3.0
0.5
2
3.3
3.3
390
35 or 50
0.3
3.6
3.6
65
32
V
V
mA
MHz
Msymbols/s
%
dB
dB
V
DDD
= 3.3 V; note 1
note 2
note 3
QPSK mode; note 1
P
tot
T
stg
T
amb
T
j
T
amb
= 70
°
C; note 1
55
0
1285
1650
+150
70
125
mW
°
C
°
C
°
C
T
amb
= 70
°
C
SYMBOL
I2
I3
V
SSD1
n.c.
n.c.
I4
I5
I6
Q0
V
DDD1
Q1
Q2
Q3
Q4
V
SSD2
Q5
Q6
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
I/O
I
I
I
I
I
I
I
I
I
I
I
I
DESCRIPTION
digital I-input bit 2 (ADC bypass); note 1
digital I-input bit 3 (ADC bypass); note 1
digital ground 1
not connected
not connected
digital I-input bit 4 (ADC bypass); note 1
digital I-input bit 5 (ADC bypass); note 1
digital I-input bit 6 (ADC bypass: MSB); note 1
digital Q-input bit 0 (ADC bypass: LSB); note 1
digital supply voltage 1
digital Q-input bit 1 (ADC bypass); note 1
digital Q-input bit 2 (ADC bypass); note 1
digital Q-input bit 3 (ADC bypass); note 1
digital Q-input bit 4 (ADC bypass); note 1
digital ground 2
digital Q-input bit 5 (ADC bypass); note 1
digital Q-input bit 6 (ADC bypass: MSB); note 1
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