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參數(shù)資料
| 型號： | TDA8044A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Satellite demodulator and decoder |
| 中文描述： | 衛(wèi)星解調(diào)器和解碼器 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 100K |
| 代理商： | TDA8044A |
2000 Feb 21
4
Philips Semiconductors
Product specification
Satellite demodulator and decoder
TDA8044
QUICK REFERENCE DATA
Notes
1.
Programmable internal frequencies possible:
a) Values 10.7, 16, 32 or 64 MHz for CFS = 0.
b) Values 16, 24, 48 or 96 MHz for CFS = 1.
CFS is set to logic 0.
Without switching internal clock frequencies, a range of 1 decade can be covered. To cover the full range of symbol
frequencies, internal clock frequencies and external (SAW) filters must be switched. Details can be found in the
application note.
Maximum value is specified for a symbol rate of 45 Msymbols/s, a puncturing rate of
7
8
, a clock frequency of 96 MHz
and a 3.55 V power supply. The typical value is specified for a symbol rate of 27.5 Msymbols/s, a puncture rate of
3
4
and a clock frequency of 64 MHz.
Implementation loss at the demodulator output and minimum S/N to lock the TDA8044 are measured including tuner
in a laboratory environment at a symbol rate of 27.5 Msymbols/s and a clock frequency of 64 MHz.
2.
3.
4.
5.
ORDERING INFORMATION
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DDA
V
DDD
I
DD(tot)
analog supply voltage
digital supply voltage
total supply current
TDA8044
TDA8044A
internal clock frequency
3.05
3.05
3.3
3.3
3.55
3.55
V
V
V
DDD
= 3.3 V
note 1
notes 1 and 2
CFS = 0 or CFS = 1;
f
xtal
= 4 MHz
note 1
notes 1 and 2
note 3
320
480
350
mA
mA
f
clk
TDA8044
TDA8044A
symbol rate
TDA8044
TDA8044A
total power dissipation
TDA8044
TDA8044A
implementation loss
signal-to-noise ratio for locking
the TDA8044
10.7
10.7
96
64
MHz
MHz
r
s
0.5
0.5
45
30
Msymbols/s
Msymbols/s
P
tot
T
amb
= 70
°
C; note 4
2
1150
0.3
1700
1250
mW
mW
dB
dB
IL
S/N
note 5
note 5
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
TDA8044H
TDA8044AH
QFP100
plastic quad flat package; 100 leads (lead length 1.95 mm);
body 14
×
20
×
2.8 mm
SOT317-2
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