參數(shù)資料
型號(hào)： TDA8044H
廠商： NXP SEMICONDUCTORS
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Satellite demodulator and decoder
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： 14 X 20 MM, 2.80 MM HEIGHT, PLASTIC, SOT-317-2, QFP-100
文件頁(yè)數(shù)： 5/20頁(yè)
文件大?。?/td> 100K
代理商： TDA8044H
2000 Feb 21
5
Philips Semiconductors
Product specification
Satellite demodulator and decoder
TDA8044
PINNING
SYMBOL
PIN
I/O
DESCRIPTION
I2
I3
V
SSD1
CFS
V
SSD2
I4
I5
I6
Q0
V
DDD1
Q1
Q2
Q3
Q4
V
SSD3
Q5
Q6
V
SSD4
V
DDD2
PRESET
P3
P2
P1
P0
V
DDD3
P5
P4
PDOCLK
PDO0
PDO1
PDO2
V
SSD5
PDO3
PDO4
PDO5
V
SSD6
V
SSD7
PDO6
POR
V
DDD4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I
I
I
I
I
I
I
I
I
I
I
I
I
I
digital I-input bit 2 (ADC bypass)
digital I-input bit 3 (ADC bypass)
digital ground 1
clock frequency selection (remains at logic 0 for TDA8044A)
digital ground 2
digital I-input bit 4 (ADC bypass)
digital I-input bit 5 (ADC bypass)
digital I-input bit 6 (ADC bypass: MSB)
digital Q-input bit 0 (ADC bypass: LSB)
digital supply voltage 1
digital Q-input bit 1 (ADC bypass)
digital Q-input bit 2 (ADC bypass)
digital Q-input bit 3 (ADC bypass)
digital Q-input bit 4 (ADC bypass)
digital ground 3
digital Q-input bit 5 (ADC bypass)
digital Q-input bit 6 (ADC bypass: MSB)
digital ground 4
digital supply voltage 2
set device into default mode
quasi-bidirectional I/O port (bit 3)
quasi-bidirectional I/O port (bit 2)
quasi-bidirectional I/O port (bit 1)
quasi-bidirectional I/O port (bit 0)
digital supply voltage 3
quasi-bidirectional I/O port (bit 5)
quasi-bidirectional I/O port (bit 4)
output clock for transport stream bytes
parallel data output (bit 0)
parallel data output (bit 1)
parallel data output (bit 2)
digital ground 5
parallel data output (bit 3)
parallel data output (bit 4)
parallel data output (bit 5)
digital ground 6
digital ground 7
parallel data output (bit 6)
Power-on reset [can be connected to PRESET (pin 20)]
digital supply voltage 4
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
I
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