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參數(shù)資料
| 型號(hào)： | TDA8315T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | Integrated NTSC decoder and sync processor |
| 中文描述： | COLOR SIGNAL DECODER, PDSO24 |
| 封裝： | 7.50 MM, PLASTIC, MS-013AD, SOT-137-1, SOP-24 |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大?。?/td> | 83K |
| 代理商： | TDA8315T |
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September 1994
9
Philips Semiconductors
Preliminary specification
Integrated NTSC decoder
and sync processor
TDA8315T
H
ORIZONTAL
PLL;
NOTE
12 (
FILTER CONNECTED TO PIN
4)
f
HR
f
CR
S/N
holding range PLL
catching range PLL
signal-to-noise ratio of the video input
signal at which the time constant is
switched
hysteresis at the switching point
±
0.6
±
0.9
±
0.9
20
±
1.2
kHz
kHz
dB
note 2
HYS
3
dB
H
ORIZONTAL OUTPUT
(
PIN
2)
V
OH
V
OL
I
O(sink)
I
O(source)
t
W
t
d
HIGH level output voltage
LOW level output voltage
output sink current
output source current
pulse width
delay time between positive edge of the
horizontal output pulse and start of the
horizontal sync pulse at the input
I
O
= 2 mA
I
O
= 2 mA
2.4
4.0
0.3
5.4
0
0.6
2
2
V
V
mA
mA
μ
s
μ
s
note 13
B
ACK PORCH CLAMPING OUTPUT
(
PIN
10)
V
OH
V
OL
I
O(sink)
I
O(source)
t
W
t
d
HIGH level output voltage
LOW level output voltage
output sink current
output source current
pulse width
delay time between start of clamping pulse
and start of the start sync pulse
I
O
= 2 mA
I
O
= 2 mA
2.4
3.2
5.2
4.0
0.3
3.4
5.4
0.6
2
2
3.6
5.6
V
V
mA
mA
μ
s
μ
s
V
ERTICAL OUTPUT
(
PIN
7);
NOTE
14
f
fr
f
lock
free-running frequency
locking range
divider value not locked
locking range (lines/frame)
HIGH level output voltage
LOW level output voltage
output sink current
output source current
pulse width (6 line periods)
delay time between start of the vertical sync
pulse at the input and the positive edge of
the output pulse
54.6
488
2.4
60
525
4.0
0.3
380
37.5
64.5
576
0.6
2
2
Hz
Hz
V
OH
V
OL
I
O(sink)
I
O(source)
t
W
t
d
I
O
= 2 mA
I
O
= 2 mA
V
V
mA
mA
μ
s
μ
s
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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