參數(shù)資料
型號: TDA8705T-T
廠商: NXP SEMICONDUCTORS
元件分類: ADC
英文描述: DUAL 2-CH 6-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28
文件頁數(shù): 14/16頁
文件大小: 93K
代理商: TDA8705T-T
1996 Jan 12
7
Philips Semiconductors
Product specication
6-bit high-speed dual Analog-to-Digital
Converter (ADC)
TDA8705
Switching characteristics
CLOCK INPUT CLK; note 1; see Fig.3
fclk(max)
maximum clock frequency
40
MHz
tCPH
clock pulse width HIGH
10
ns
tCPL
clock pulse width LOW
10
ns
Analog signal processing
LINEARITY
ILE
DC integral linearity error
±0.25
±0.5
LSB
DLE
DC differential linearity error
±0.25
±0.5
LSB
AILE
AC integral linearity error
note 3
±0.5
±1.0
LSB
OFE
offset error between A and B
fi = 10 MHz;
fclk = 40 MHz; note 4
±1
±2
LSB
GE
gain error between A and B
fi = 10 MHz;
fclk = 40 MHz; note 4
±1
±2
LSB
MID
middle scale output code A and B
input voltage oating
31
32
BANDWIDTH;fclk =40MHz
B
0.5 dB analog bandwidth
full-scale sine wave;
note 5
50
MHz
tSTLH
analog input settling time LOW-to-HIGH
full-scale square wave;
Fig.4; note 6
8
ns
tSTHL
analog input settling time HIGH-to-LOW
full-scale square wave;
Fig.4; note 6
5
ns
HARMONICS;fclk =40MHZ; see Fig.5
h1
fundamental harmonics (full scale)
fi = 10 MHz
0dB
hall
harmonics (full scale);
all components
fi = 10 MHz
second harmonics
49
dB
third harmonics
51
dB
THD
total harmonic distortion
fi = 10 MHz
46
40
dB
SIGNAL-TO-NOISE RATIO; note 7; see Fig.5
S/N
signal-to-noise ratio (full scale)
without harmonics;
fclk = 40 MHz;
fi = 10 MHz
34
37
dB
EFFECTIVE BITS; note 7; see Figs 5 and 6
EB
effective bits
fclk = 40 MHz
fi = 10 MHz
5.8
bits
fi = 20 MHz
5.6
bits
TWO-TONE; note 8
TTIR
two-tone intermodulation rejection
fclk = 40 MHz
48
dB
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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