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參數(shù)資料
| 型號(hào)： | TDA8798HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | Dual 8-bit, 100 Msps A/D converter with DPGA |
| 中文描述： | DUAL 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁(yè)數(shù)： | 13/24頁(yè) |
| 文件大?。?/td> | 195K |
| 代理商： | TDA8798HL |
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1999 Sep 16
13
Philips Semiconductors
Objective specification
Dual 8-bit, 100 Msps A/D converter with
DPGA
TDA8798
D
IGITAL OUTPUTS
(A0
TO
A7
AND
B0
TO
B7)
V
OL
V
OH
I
OZ
LOW-level output voltage
HIGH-level output voltage
output current in 3-state mode V
O
> 0.4 V;
I
O
= 1 mA
I
O
=
1 mA
V
DDO
0.4 V
20
0.4
+20
V
V
μ
A
V
O
< (V
DDO
0.4 V)
ADC
CLOCK TIMING
f
CLK(max)
t
W(CLKL)
maximum clock frequency
clock pulse width LOW
duration
clock pulse width HIGH
duration
clock pulse rise time
clock pulse fall time
100
4.0
MHz
ns
t
W(CLKH)
4.0
ns
t
r(CLK)
t
f(CLK)
D
ATA TIMING
(see Fig.4);
F
CLK
= 100 MH
Z
; C
DPGAC
= 10
P
F
t
d(s)(D)
data sampling delay time
t
d(Q)
data output delay time
0.75
0.75
1
1
2
2
ns
ns
tbf
tbf
5.0
tbf
5.0
tbf
tbf
tbf
tbf
ns
ns
ns
ns
ns
SR HIGH
SR LOW
SR HIGH
SR LOW
t
h(Q)
data output hold time
3-
STATE OUTPUT DELAY TIMES
(see Fig.6)
t
dZH
output delay enable at logic
HIGH
SR HIGH
SR LOW
SR HIGH
SR LOW
SR HIGH
SR LOW
SR HIGH
SR LOW
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
tbf
ns
ns
ns
ns
ns
ns
ns
ns
t
dZL
output delay enable at logic
LOW
t
dHZ
output delay disable at logic
HIGH
t
dLZ
output delay disable at logic
LOW
ADC R
EFERENCE OUTPUTS
(V
REF
1
AND
V
REF
2
)
V
o(ref)
ADC reference output voltage
R
o(ref)
ADC reference output
resistance
I
o(ref)(max)
ADC reference maximum
output current
C
o(ref)
ADC reference output
capacitance
1.24
10
V
at V
o(ref)
4.0
mA
3
pF
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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