參數(shù)資料
型號(hào)： TDA8840-N2
廠商： NXP Semiconductors N.V.
英文描述： I2C-bus controlled PAL/NTSC/SECAM TV processors
中文描述： I2C總線控制的PAL / NTSC制式/ SECAM電視處理器
文件頁數(shù)： 23/68頁
文件大小： 316K
代理商： TDA8840-N2
December 16, 1997
23
Philips Semiconductors
Tentative Device Specification
I
2
C-bus controlled PAL/NTSC/SECAM TV
processors
TDA884X/5X-N2 series
Table 50
Bypass of chroma base-band delay line
Table 51
Automatic colour limiting
Table 52
Enable external comb filter
Table 53
Start-up mode of black current loop; note 1
Note
1.
When the circuit is in the automatic mode the RGB
drive is switched-on as soon as the black current loop
has stabilised. Under control of the
μ
-processor the
condition of the black current loop is indicated via the
BCF bit. When this bit changes to 0 the RGB drive can
be switched-on by setting the AST bit to 0.
BPS
DELAY LINE MODE
0
1
active
bypassed
ACL
COLOUR LIMITING
0
1
not active
active
CMB
COMB FILTER
0
1
disabled
enabled
AST
MODE
0
1
automatic mode;
switch-on under control of
μ
-processor
Table 54
Cathode drive level
Note
1.
The given values are valid for the following conditions:
- Nominal CVBS input signal
- Settings for contrast, WPA and peaking nominal
- Black- and blue-stretch switched-off
- Gain of output stage such that no clipping occurs
- Beam current limiting not active
The tolerance on these values is about
±
3 V.
Table 55
Y-delay adjustment; note 1
Note
1.
For an equal delay of the luminance and chrominance
signal the delay must be set at a value of 160 ns. This
is only valid for a CVBS signal without group
delay distortions.
Table 56
Dynamic skin control on/off
Table 57
Dynamic skin control angle
CL2
CL1
CL0
SETTING CATHODE DRIVE
AMPLITUDE; NOTE
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
57V
BL-WH
63 V
BL-WH
70 V
BL-WH
77 V
BL-WH
84 V
BL-WH
91 V
BL-WH
99 V
BL-WH
107 V
BL-WH
YD0 to YD3
Y-DELAY
YD3
YD2
YD1
YD0
YD3
160 ns +
YD2
80 ns +
YD1
40 ns +
YD0
40 ns
DS
MODE
0
1
off
on
DSA
ANGLE OF CORRECTION
0
1
correction angle 123 degrees
correction angle 117 degrees
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