參數(shù)資料
型號(hào)： TDA8842-N2
廠商： NXP Semiconductors N.V.
英文描述： I2C-bus controlled PAL/NTSC/SECAM TV processors
中文描述： I2C總線控制的PAL / NTSC制式/ SECAM電視處理器
文件頁數(shù)： 43/68頁
文件大小： 316K
代理商： TDA8842-N2
December 16, 1997
43
Philips Semiconductors
Tentative Device Specification
I
2
C-bus controlled PAL/NTSC/SECAM TV
processors
TDA884X/5X-N2 series
Notes
1.
2.
On set AGC.
This parameter is not tested during production and is just given as application information for the designer of the
television receiver.
Loop bandwidth BL = 60 kHz (natural frequency fN = 15 kHz; damping factor d = 2; calculated with top sync level as
FPLL input signal level).
The IF-PLL demodulator uses an internal VCO (no external LC-circuit required) which is calibrated by means of a
digital control circuit which uses the X-tal frequency of the colour decoder as a reference. The required IF frequency
for the various standards is set via the I
2
C-bus (IFA-IFC bits in sub-address 15H). When the system is locked the
resulting IF frequency is very accurate with a deviation from the nominal value of less than 25 kHz.
This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix
batches which are made in the pilot production period.
Measured at 10 mV (RMS) top sync input signal.
So called projected zero point, i.e. with switched demodulator.
Measured in accordance with the test line given in Fig.14. For the differential phase test the peak white setting is
reduced to 87%.
The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and
smallest value relative to the subcarrier amplitude at blanking level.
The phase difference is defined as the difference in degrees between the largest and smallest phase angle.
3.
4.
5.
6.
7.
8.
BEAM CURRENT LIMITING
(
CONTINUED
)
C.7.4
voltage difference for full
brightness reduction
internal bias voltage
detection level vertical guard
minimum input current to
activate the guard circuit
maximum allowable current
1
V
C.7.5
C.7.6
C.7.7
3.3
3.65
100
V
V
μ
A
C.7.8
1
mA
BLUE STRETCH
;
NOTE
53
C.8.1
decrease of small signal gain for
the red and green channel
decrease of small signal gain for
the red channel
decrease of small signal gain for
the green channel
BLS = 1
14
%
C.8.2
EBS = 1
22
%
C.8.3
EBS = 1
8
%
I
2
C-BUS CONTROL INPUT/OUTPUT (SDA/SCL)
B.1.1
B.1.2
B.1.3
B.1.4
B.1.5
B.1.6
input voltage level
low-level input voltage
high-level input voltage
low-level input current
high-level input current
low-level output voltage
0
3.5
5.5
1.5
-10
10
0.4
V
V
V
μ
A
μ
A
V
V
i
= 0 V
V
i
= 5.5 V
SDA, I
L
= 3 mA
NUMBER
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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