參數(shù)資料
型號： TDA8843-N2
廠商： NXP Semiconductors N.V.
英文描述： I2C-bus controlled PAL/NTSC/SECAM TV processors
中文描述： I2C總線控制的PAL / NTSC制式/ SECAM電視處理器
文件頁數(shù)： 45/68頁
文件大?。?/td> 316K
代理商： TDA8843-N2
December 16, 1997
45
Philips Semiconductors
Tentative Device Specification
I
2
C-bus controlled PAL/NTSC/SECAM TV
processors
TDA884X/5X-N2 series
26. Several versions have a YUV interface. The luminance and colour difference out- and inputs can directly be
connected. When additional picture improvement IC’s (like the TDA 9170) are applied the inputs of these IC’s must
be ac coupled because of the black level clamp requirement. The output signal of the picture improvement IC can
directly be coupled to the luminance and colour difference inputs as long as the dc level of these signals have a value
between 1 and 7 Volts (for the luminance signal) or between 1 and 4 Volts (for the UV signals). When the dc level of
the input signals exceed these levels the signals must be ac coupled and biased to a voltage level within these limits.
To be able to apply CTI IC’s like the TDA 4565/66 the gain of the luminance channel can be increased via the setting
of the GAI bit in the I
2
C subaddress 03.
27. When the decoder is forced to a fixed subcarrier frequency (via XA/XB or the CM-bits) the chroma trap is always
switched-on, also when no colour signal is identified. When 2 X-tals are active the chroma trap is switched-off when
no colour signal is identified.
28. Valid for a signal amplitude on the Y-input of 0.7 V black-to-white (100 IRE) with a rise time (10% to 90%) of 70 ns
and the video switch in the Y/C mode. During production the peaking function is not tested by measuring the
overshoots but by measuring the frequency response of the Y output.
29. For video signals with a black level which deviates from the back-porch blanking level the signal is “stretched” to the
blanking level. The amount of correction depends on the IRE value of the signal (see Fig.19). The black level is
detected by means of an internal capacitor. The black level stretcher can be switched on and off via the BKS bit in
the I
2
C-bus. The values given in the specification are valid only when the luminance input signal has an amplitude
of 1 V
p-p
.
30. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing
level and the black level (back porch). When the amplitude of the sync pulse exceeds the value of 350 mV the sync
separator will slice the sync pulse at a level of 175 mV above top sync. The maximum sync pulse amplitude is 4 V
p-p
.
31. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is
switched depending on the input signal condition and the condition of the I
2
C-bus. Therefore the circuit contains a
noise detector and the time constant is switched to ‘slow’ when too much noise is present in the signal. In the ‘fast’
mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to
head-switching of the VCR are corrected as soon as possible. Switching between the two modes can be
automatically or overruled by the I
2
C-bus.
The circuit contains a video identification circuit which is independent of first loop. This identification circuit can be
used to close or open the first control loop when a video signal is present or not present on the input. This enables
a stable On Screen Display (OSD) when just noise is present at the input. The coupling of the video identification
circuit with the first loop can be defeated via the I
2
C-bus.
To prevent that the horizontal synchronisation is disturbed by anti copy signals like Macrovision the phase detector
is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage. The width
of the gate pulse is about 22
μ
s. During weak signal conditions (noise detector active) the gating is active during the
complete scan period and the width of the gate pulse is reduced to 5.7
μ
s so that the effect of noise is reduced to a
minimum.
The output current of the phase detector in the various conditions are shown in Table 75.
32. The IC’s have 2 protection inputs. The protection on pin 42 is intended to be used as “flash” protection. When this
protection is activated the horizontal drive is switched-off immediately and then switched-on again via the slow start
procedure.
The protection on pin 50 is intended for overvoltage (X-ray) protection. When this protection is activated the
horizontal drive can directly be switched-off (via the slow stop procedure). It is also possible to continue the horizontal
drive and to set the protection bit (XPR) in the output bytes of the I
2
C-bus. The choice between the 2 modes of
operation is made via the PRD bit.
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